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PDF SI53360 Data sheet ( Hoja de datos )
| Número de pieza | SI53360 | |
| Descripción | 1:8 LOW JITTER CMOS CLOCK BUFFER | |
| Fabricantes | Silicon Laboratories | |
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Si53360
1:8 LOW JITTER CMOS CLOCK BUFFER
WITH 2:1 INPUT MUX (<200 MHZ)
Features
8 LVCMOS outputs
Low additive jitter: 150 fs rms typ
Wide-frequency range:
dc to 200 MHz
2:1 input MUX
Asynchronous output enable
Low output-output skew: 40 ps typ
RoHs compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Footprint-compatible with ICS552-02
1.8, 2.5, or 3.3 V operation
16-TSSOP
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53360 is an ultra low jitter eight output LVCMOS buffer. The Si53360
features a 2:1 input mux, making it ideal for redundant clocking applications. The
Si53360 utilizes Silicon Laboratories’ advanced CMOS technology to fanout
clocks from dc to 200 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53360 supports operation over the industrial
temperature range and can be operated from a 1.8 V, 2.5 V, or 3.3 V supply.
Functional Block Diagram
Ordering Information:
See page 10.
Pin Assignments
OE 1
VDD 2
Q0 3
Q1 4
Q2 5
16 CLK_SEL
15 VDD
14 Q7
13 Q6
12 Q5
Q3 6
11 Q4
VDD
Power
Supply
Filtering
Q0
Q1
GND 7
CLK0 8
10 GND
9 CLK1
CLK0
0
Q2
Q3
Patents pending
CLK1
CLK_SEL
1
Q4
Q5
Q6
Q7
GND OE
Rev. 1.1 8/15
Copyright © 2015 by Silicon Laboratories
Si53360
1 page  
Si53360
Table 6. Thermal Conditions
Parameter
Thermal Resistance,
Junction to Ambient
Symbol
JA
Test Condition
Still air
Value
124.4
Unit
°C/W
Table 7. Absolute Maximum Ratings
Parameter
Storage Temperature
Supply Voltage
Input Voltage
Symbol
TS
VDD
VIN
Test Condition
Min
–55
–0.5
–0.5
Typ Max
— 150
— 3.8
— VDD+
0.3
Unit
C
V
V
Output Voltage
VOUT
— — VDD+ V
0.3
ESD Sensitivity
HBM
HBM, 100 pF, 1.5 kΩ
— — 2000 V
ESD Sensitivity
CDM
— — 500
V
Peak Soldering Reflow TPEAK
Temperature
Pb-Free; Solder reflow profile
per JEDEC J-STD-020
—
— 260
C
Maximum Junction
Temperature
TJ
— — 125 C
Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Rev. 1.1
5
5 Page 
5. Package Outline
5.1. 16-TSSOP Package Diagram
Si53360
Figure 4. Si53360 16-TSSOP Package Diagram
Table 10. Package Dimensions
Dimension
A
A1
A2
Min
—
0.05
0.80
Nom
—
—
1.00
Max
1.20
0.15
1.05
Dimension
e
L
L2
Min
0.45
Nom
0.65 BSC
0.60
0.25 BSC
Max
0.75
b 0.19 — 0.30
0 — 8
c 0.09 — 0.20
aaa
0.10
D
4.90
5.00 5.10
E 6.40 BSC
bbb
ccc
0.10
0.20
E1
4.30
4.40 4.50
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
Rev. 1.1
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet SI53360.PDF ] | |
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