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PDF SI53315 Data sheet ( Hoja de datos )
| Número de pieza | SI53315 | |
| Descripción | 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR | |
| Fabricantes | Silicon Laboratories | |
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Si53315
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE (<1.25 GHZ)
Features
10 differential or 20 LVCMOS outputs Low propagation delay variation:
Ultra-low additive jitter: 100 fs rms
<400 ps
Wide frequency range:
1 MHz to 1.25 GHz
Independent VDD and VDDO :
1.8/2.5/3.3 V
Any-format input with pin selectable Excellent power supply noise
output formats: LVPECL, Low Power rejection (PSRR)
LVPECL, LVDS, CML, HCSL,
LVCMOS
Selectable LVCMOS drive strength to
tailor jitter and EMI performance
2:1 mux with hot-swappable inputs Small size: 44-QFN (7 mm x 7 mm)
Asynchronous output enable
RoHS compliant, Pb-free
Individual output enable
Industrial temperature range:
Low output-output skew: <50 ps
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53315 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53315 features a 2:1 mux,
making it ideal for redundant clocking applications. The Si53315 utilizes Silicon
Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to
1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay
variability. The Si53315 features minimal cross-talk and provides superior supply
noise rejection, simplifying low jitter clock distribution in noisy environments.
Independent core and output bank supply pins provide integrated level translation
without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 25.
Pin Assignments
Si53315
OE2 1
SFOUT[0] 2
OE1 3
Q2 4
Q2 5
GND 6
Q1 7
Q1 8
Q0 9
Q0 10
OE0 11
GND
PAD
33 OE7
32 SFOUT[1]
31 OE8
30 Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 OE9
Patents pending
VREF
Vref
Generator
Power
Supply
Filtering
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Switching
Logic
VDDOA
OE[0:4]
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
SFOUT[1:0]
VDDOB
OE[5:9]
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Preliminary Rev. 0.4 10/12
Copyright © 2012 by Silicon Laboratories
Si53315
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
1 page  
Si53315
Table 4. DC Characteristics—LVPECL and Low Power LVPECL
(VDD = 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Parameter
Output Voltage High
Symbol
VOH
Test Condition
RL = 50 Ω to VDDOX – 2 V
Min
VDDOX –
1.145
Output Voltage Low
VOL
RL = 50 Ω to VDDOX – 2 V
VDDOX –
1.945
Output DC Common
Mode Voltage
VCOM
VDDOX –
1.895
Single-Ended
Output Swing
VSE Terminate unused outputs to 0.25
RL = 50 Ω to VDDOX – 2 V
Typ
—
—
—
0.60
Max
VDDOX –
0.895
VDDOX –
1.695
VDDOX –
1.425
0.85
Unit
V
V
V
V
Table 5. DC Characteristics—CML
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Parameter
Single-Ended Output
Swing
Symbol
VSE
Test Condition
Terminated as shown in Figure 6
(CML termination).
Min
300
Typ Max Unit
400 500
mV
Table 6. DC Characteristics—LVDS
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(VDDO = 2.5 V or
3.3 V)
Output Common
Mode Voltage
(VDDO = 1.8 V)
Symbol
VSE
VCOM1
VCOM2
Test Condition
RL = 100 Ω across QN and QN
VDDOX = 2.38 to 2.63 V, 2.97 to
3.63 V, RL = 100 Ω across QN
and QN
VDDOX = 1.71 to 1.89 V,
RL = 100 Ω across QN
and QN
Min
247
1.10
0.85
Typ Max
— 454
1.25 1.35
0.97 1.10
Unit
mV
V
V
Preliminary Rev. 0.4
5
5 Page 
Si53315
DC Coupled LVPECL Termination Scheme 1
VDDO
VDDO = 3.3V or 2.5V
R1 R1
“Standard”
LVPECL
Driver
50
50
CLKx
/CLKx
VDD
Si533xx
3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm
2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm
R2
R2
VTERM = VDDO – 2V
R1 // R2 = 50 Ohm
DC Coupled LVPECL Termination Scheme 2
VDDO = 3.3V or 2.5V
“Standard”
LVPECL
Driver
50
50
50 50
CLKx
/CLKx
VDD
Si533xx
VTERM = VDDO – 2V
DC Coupled LVDS Termination
VDDO = 3.3V or 2.5V
Standard
LVDS
Driver
50
50
CLKx
/CLKx
100
VDD
Si533xx
DC Coupled HCSL Termination Scheme
VDDO = 3.3V
Standard
HCSL Driver
33
33
50
50
50 50
VDD
CLKx
/CLKx
Si533xx
Note: 33 Ohm series termination is optional depending on the location of the receiver.
Figure 3. Differential DC-Coupled Input Terminations
Preliminary Rev. 0.4
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53315.PDF ] | |
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