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PDF SI53308 Data sheet ( Hoja de datos )
| Número de pieza | SI53308 | |
| Descripción | DUAL 1:3 LOW-JITTER BUFFER/LEVEL TRANSLATOR | |
| Fabricantes | Silicon Laboratories | |
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Si53308
DUAL 1:3 LOW-JITTER BUFFER/LEVEL TRANSLATOR
Features
6 differential or 12 (in phase)
Loss of signal (LOS) monitors for
LVCMOS outputs
loss of input clock
Ultra-low additive jitter: 45 fs rms Independent VDD and VDDO :
Wide frequency range: 1 to 725 MHz 1.8/2.5/3.3 V
Any-format input with pin selectable Selectable LVCMOS drive strength to
output formats: LVPECL, low power tailor jitter and EMI performance
LVPECL, LVDS, CML, HCSL,
LVCMOS
Synchronous output enable
Output clock division: /1, /2, /4
Low output-output skew: 25 ps
Small size: 32-QFN (5 mm x 5 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53308 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and divider selection. The device is a dual 1:3 buffer
providing the functionality of two independent buffers in a single IC. The Si53308
utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1
to 725 MHz with guaranteed low additive jitter, low skew, and low propagation
delay variability. The Si53308 features minimal cross-talk and provides superior
supply noise rejection, simplifying low jitter clock distribution in noisy
environments. Independent core and output bank supply pins provide integrated
level translation without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 28.
Pin Assignments
Si53308
DIVA 1
SFOUTA[1] 2
SFOUTA[0] 3
Q0 4
Q0 5
GND 6
VDD 7
NC 8
GND
PAD
24 DIVB
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
Patents pending
VREF
CLK0
CLK0
Vref
Generator
Power
Supply
Filtering
DivA
CLK1
CLK1
DivB
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2
Q0, Q1, Q2
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q3, Q4, Q5
Q3, Q4, Q5
Rev. 0.9 6/13
Copyright © 2013 by Silicon Laboratories
Si53308
1 page  
Si53308
Table 3. DC Common Characteristics
(VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min Typ Max
Supply Current
Output Buffer
Supply Current
(Per Clock Output)
@100 MHz (diff)
@200 MHz (CMOS)
IDD
IDDOX
LVPECL (3.3 V)
Low Power LVPECL (3.3 V)*
LVDS (3.3 V)
CML (3.3 V)
—
—
—
—
—
65 100
35 —
35 —
20 —
35 —
HCSL, 100 MHz, 2 pF load
—
35
—
(3.3 V)
Voltage Reference
Input High Voltage
Input Mid Voltage
VREF
VIH
VIM
CMOS (2.5 V, SFOUT = Open/0),
per output, CL = 5 pF, 200 MHz
CMOS (3.3 V, SFOUT = 0/1),
per output, CL = 5 pF, 200 MHz
VREF pin (VDD = 2.5/3.3 V)
—
—
—
8
15
VDD/2
—
—
—
SFOUTX, DIVX, OEX
0.8xVDD
—
—
SFOUTX, DIVX
3-level input pins
0.45xVDD 0.5xVDD 0.55xVDD
Input Low Voltage
VIL
SFOUTX, DIVX, OEX
— — 0.2xVDD
Output Voltage High VOH
IDD = –1 mA
0.8xVDD
—
—
Output Voltage Low
VOL
IDD = 1 mA
— — 0.2xVDD
Internal Pull-down
Resistor
RDOWN
DIVX, SFOUTX
— 25 —
Internal Pull-up
Resistor
RUP
DIVX, SFOUTX, OEX
— 25 —
*Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power.
Unit
mA
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
k
k
Rev. 0.9
5
5 Page 
Si53308
Table 12. Additive Jitter, Single-Ended Clock Input
VDD
Input1,2
Output
Freq
(MHz)
Clock Format
Amplitude
VIN
(single-ended,
peak to peak)
SE 20%-80%
Slew Rate
(V/ns)
Clock Format
3.3 200 Single-ended
1.70
1 LVCMOS4
3.3 156.25 Single-ended
2.18
1 LVPECL
3.3 156.25 Single-ended
2.18
1 LVDS
3.3 156.25 Single-ended
2.18
1 LVCMOS4
2.5 200 Single-ended
1.70
1 LVCMOS5
2.5 156.25 Single-ended
2.18
1 LVPECL
2.5 156.25 Single-ended
2.18
1 LVDS
2.5 156.25 Single-ended
2.18
1 LVCMOS5
Additive Jitter
(fs rms, 12 kHz to
20 MHz)3
Typ Max
120 160
160 185
150 200
130 180
120 160
145 185
145 195
140 180
Notes:
1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock
Buffer’s Additive Jitter Performance” for more information.
2. DC-coupled single-ended inputs.
3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. LVCMOS jitter is measured
single-ended.
4. Drive Strength: 12 mA, 3.3 V (SFOUT = 11).
5. Drive Strength: 9 mA, 2.5 V (SFOUT = 11).
CLK SYNTH
SMA103A
PSPL 5310A
Balun
Si533xx
DUT
CLKx
/CLKx
50
50
PSPL 5310A
Balun
AG E5052 Phase Noise
Analyzer
50ohm
Figure 1. Differential Measurement Method Using a Balun
Rev. 0.9
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53308.PDF ] | |
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