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PDF SI53301 Data sheet ( Hoja de datos )
| Número de pieza | SI53301 | |
| Descripción | 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR | |
| Fabricantes | Silicon Laboratories | |
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Si53301
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX
Features
6 differential or 12 LVCMOS outputs Loss of signal (LOS) monitors for
Ultra-low additive jitter: 45 fs rms
loss of input clock
Wide frequency range: 1 to 725 MHz Independent VDD and VDDO :
Universal any-format input with pin
1.8/2.5/3.3 V
selectable output formats
1.2/1.5 V LVCMOS output support
LVPECL, low power LVPECL, LVDS, Selectable LVCMOS drive strength to
CML, HCSL, LVCMOS
tailor jitter and EMI performance
2:1 input mux
Small size: 32-QFN (5 mm x 5 mm)
Glitchless input clock switching
RoHS compliant, Pb-free
Synchronous output enable
Industrial temperature range:
Output clock division: /1, /2, /4
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53301 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and divider selection. The Si53301 features a 2:1 input
mux with glitchless switching, making it ideal for redundant clocking applications.
The Si53301 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53301 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
Ordering Information:
See page 29.
Pin Assignments
Si53301
DIVA
SFOUTA[1]
SFOUTA[0]
Q0
Q0
GND
VDD
CLK_SEL
1
2
3
4
5
6
7
8
GND
PAD
24 DIVB
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
Patents pending
Vref
LOS0
LOS1
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
VDD
Vref
Generator
LOS
Monitor
Power
Supply
Filtering
DivA
BANK A
Switching
Logic
DivB
BANK B
DIVA
VDDOA
SFOUTA[1:0]
OEA
Q0, Q1, Q2
/Q0, /Q1, /Q2
DIVB
VDDOB
SFOUTB[1:0]
OEB
Q3, Q4, Q5
/Q3, /Q4, /Q5
Rev. 1.1 6/14
Copyright © 2014 by Silicon Laboratories
Si53301
1 page  
Si53301
Table 4. Output Characteristics (LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Output DC Common Mode
Voltage
VCOM
VDDOX – 1.595
Single-Ended
Output Swing*
VSE
0.55
*Note: Unused outputs can be left floating. Do not short unused outputs to ground.
Typ
—
0.80
Max
Unit
VDDOX – 1.245 V
1.050
V
Table 5. Output Characteristics (Low Power LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Output DC Common VCOM RL = 100 across Qn and Qn VDDOX – 1.895
Mode Voltage
Single-Ended
Output Swing
VSE RL = 100 across Qn and Qn
0.25
Typ
0.60
Max
Unit
VDDOX – 1.275 V
0.85 V
Table 6. Output Characteristics—CML
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
VSE
Test Condition
Terminated as shown in Figure 9
(CML termination).
Min
300
Typ Max Unit
400 550
mV
Table 7. Output Characteristics—LVDS
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(VDDO = 2.5 V or
3.3V)
Output Common
Mode Voltage
(VDDO = 1.8 V)
Symbol
VSE
VCOM1
VCOM2
Test Condition
RL = 100 Ω across QN and QN
VDDOX = 2.38 to 2.63 V, 2.97 to
3.63 V, RL = 100 Ω across QN
and QN
VDDOX = 1.71 to 1.89 V,
RL = 100 Ω across QN
and QN
Min
247
1.10
0.85
Typ Max
— 490
1.25 1.35
0.97 1.25
Unit
mV
V
V
Rev. 1.1
5
5 Page 
Si53301
Table 13. Thermal Conditions
Parameter
Thermal Resistance,
Junction to Ambient
Thermal Resistance,
Junction to Case
Symbol
JA
JC
Test Condition
Still air
Still air
Value
49.6
32.3
Unit
°C/W
°C/W
Table 14. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min Typ Max Unit
Storage Temperature
Supply Voltage
Input Voltage
Output Voltage
ESD Sensitivity
TS
VDD
VIN
VOUT
HBM
HBM, 100 pF, 1.5 k
–55 —
150
–0.5 —
3.8
–0.5 — VDD+ 0.3
— — VDD+ 0.3
——
2000
C
V
V
V
V
ESD Sensitivity
CDM
——
500
V
Peak Soldering
Reflow Temperature
TPEAK Pb-Free; Solder reflow profile
per JEDEC J-STD-020
—
—
260
C
Maximum Junction
Temperature
TJ
——
125
C
Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Rev. 1.1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53301.PDF ] | |
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