PDF SI53307 Data sheet ( Hoja de datos )

Número de pieza	SI53307
Descripción	2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR
Fabricantes	Silicon Laboratories
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No Preview Available ! Si53307 2:2 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR Features  2 differential or 4 LVCMOS outputs  2:1 input mux with glitchless input  Ultra-low additive jitter: 45 fs rms clock switching  Wide frequency range: 1 to 725 MHz  Independent VDD and VDDO :  Any-format input with pin selectable 1.8/2.5/3.3 V output formats: LVPECL, low power  Small size: 16-QFN (3 mm x 3 mm) LVPECL, LVDS, CML, HCSL,  RoHS compliant, Pb-free LVCMOS  Synchronous output enable  Industrial temperature range: –40 to +85 °C Applications  High-speed clock distribution  Ethernet switch/router  Optical Transport Network (OTN)  SONET/SDH  PCI Express Gen 1/2/3  Storage  Telecom  Industrial  Servers  Backplane clock distribution Description The Si53307 is an ultra-low jitter two output differential buffer with pin-selectable output clock signal format and 2:1 input clock mux. The Si53307 utilizes Silicon Labs' advanced CMOS technology to fanout clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53307 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. Functional Block Diagram Ordering Information: See page 26. Pin Assignments VDD 1 CLK1 2 CLK1 3 GND 4 GND PAD 12 Q0 11 Q0 10 Q1 9 Q1 Patents pending Rev. 1.0 11/14 Copyright © 2014 by Silicon Laboratories Si53307 1 page Si53307 Table 3. DC Common Characteristics (VDD = VDDO = 1.8 V 5%, 2.5 V  5%, or 3.3 V 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Supply Current IDD — 65 100 mA Output Buffer IDDO LVPECL (3.3 V) — 40 — mA Supply Current (Per Clock Output) Low Power LVPECL (3.3 V)* — 35 — mA @100 MHz (diff) LVDS (3.3 V) — 20 — mA @200 MHz (CMOS) CML (3.3 V) — 60 — mA HCSL, 100 MHz, 2 pF load — 35 — mA (3.3 V) CMOS (2.5 V, SFOUT = Open/0), — 10 — per output, CL = 5 pF, 200 MHz CMOS (3.3 V, SFOUT = 0/1), — 20 — per output, CL = 5 pF, 200 MHz Input High Voltage VIH SFOUTX, OE 0.8 x VDD — — Input Mid Voltage VIM SFOUTX, 3-level input pins 0.45 x VDD 0.5 x VDD 0.55 x VDD Input Low Voltage VIL SFOUTX, OE — — 0.2 x VDD Internal Pull-down Resistor RDOWN SFOUT, CLK_SEL — 25 — Internal Pull-up Resistor RUP SFOUTX, OE — 25 — *Note: Low-power LVPECL mode supports an output termination scheme that will reduce overall system power. mA mA V V V k k Rev. 1.0 5 5 Page Si53307 Table 13. Thermal Conditions Parameter Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Case Symbol JA JC Test Condition Still air Still air Value 57.6 41.5 Unit °C/W °C/W Table 14. Absolute Maximum Ratings Parameter Symbol Test Condition Min Typ Max Unit Storage Temperature Supply Voltage Input Voltage Output Voltage ESD Sensitivity TS VDD VIN VOUT HBM 100 pF, 1.5 k –55 –0.5 –0.5 — — — 150 — 3.8 — VDD + 0.3 — VDD + 0.3 — 2000 C V V V V ESD Sensitivity CDM —— 500 V Peak Soldering Reflow Temperature TPEAK Pb-Free; Solder reflow profile per JEDEC J-STD-020 — — 260 C Maximum Junction Temperature TJ —— 125 C Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. Rev. 1.0 11 11 Page

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