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PDF SI53305 Data sheet ( Hoja de datos )
| Número de pieza | SI53305 | |
| Descripción | 1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR | |
| Fabricantes | Silicon Laboratories | |
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Si53305
1:10 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE
Features
10 differential or 20 LVCMOS outputs Low output-output skew: <70 ps
Ultra-low additive jitter: 45 fs rms Low propagation delay variation:
Wide frequency range:
<400 ps
dc to 725 MHz
Independent VDD and VDDO :
Any-format input with pin selectable 1.8/2.5/3.3 V
output formats: LVPECL, Low Power Excellent power supply noise
LVPECL, LVDS, CML, HCSL,
rejection (PSRR)
LVCMOS
Selectable LVCMOS drive strength to
2:1 mux with hot-swappable inputs
tailor jitter and EMI performance
Glitchless input clock switching
(1 MHz to 725 MHz)
Individual output enable
Synchronous output enable
Small size: 44-QFN (7 mm x 7 mm)
RoHS compliant, Pb-free
Industrial temperature range:
–40 to +85 °C
Ordering Information:
See page 30.
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53305 is an ultra low jitter ten output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53305 features a 2:1 mux with
glitchless switching, making it ideal for redundant clocking applications. The
Si53305 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from dc to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53305 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
Pin Assignments
Si53305
OE2 1
SFOUT[0] 2
OE1 3
Q2 4
Q2 5
GND 6
Q1 7
Q1 8
Q0 9
Q0 10
OE0 11
GND
PAD
33 OE7
32 SFOUT[1]
31 OE8
30 Q7
29 Q7
28 NC
27 Q8
26 Q8
25 Q9
24 Q9
23 OE9
Patents pending
VREF
Vref
Generator
Power
Supply
Filtering
CLK0
CLK0
CLK1
CLK1
CLK_SEL
Switching
Logic
VDDOA
OE[0:4]
Q0, Q1, Q2, Q3, Q4
Q0, Q1, Q2, Q3, Q4
SFOUT[1:0]
VDDOB
OE[5:9]
Q5, Q6, Q7, Q8, Q9
Q5, Q6, Q7, Q8, Q9
Rev. 1.0 9/15
Copyright © 2015 by Silicon Laboratories
Si53305
1 page  
Si53305
Table 4. Output Characteristics (LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Output DC Common Mode
Voltage
VCOM
VDDOX – 1.595
Single-Ended
Output Swing*
VSE
0.55
*Note: Unused outputs can be left floating. Do not short unused outputs to ground.
Typ
—
0.80
Max
Unit
VDDOX – 1.245 V
1.050
V
Table 5. Output Characteristics (Low Power LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Output DC Common VCOM RL = 100 across Qn and Qn VDDOX – 1.895
Mode Voltage
Single-Ended
Output Swing
VSE RL = 100 across Qn and Qn
0.25
Typ
0.60
Max
Unit
VDDOX – 1.275 V
0.85 V
Table 6. Output Characteristics—CML
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
VSE
Test Condition
Terminated as shown in Figure 9
(CML termination).
Min
300
Typ Max Unit
400 550
mV
Rev. 1.0
5
5 Page 
Si53305
Table 13. Thermal Conditions
Parameter
Thermal Resistance,
Junction to Ambient
Thermal Resistance,
Junction to Case
Symbol
JA
JC
Test Condition
Still air
Still air
Value
49.6
32.3
Unit
°C/W
°C/W
Table 14. Absolute Maximum Ratings
Parameter
Symbol
Test Condition
Min Typ Max Unit
Storage Temperature
Supply Voltage
Input Voltage
Output Voltage
ESD Sensitivity
TS
VDD
VIN
VOUT
HBM
HBM, 100 pF, 1.5 k
–55 —
150
–0.5 —
3.8
–0.5 — VDD+ 0.3
— — VDD+ 0.3
——
2000
C
V
V
V
V
ESD Sensitivity
CDM
——
500
V
Peak Soldering
Reflow Temperature
TPEAK Pb-Free; Solder reflow profile
per JEDEC J-STD-020
—
—
260
C
Maximum Junction
Temperature
TJ
——
125
C
Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation
specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Rev. 1.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53305.PDF ] | |
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