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PDF SI53304 Data sheet ( Hoja de datos )
| Número de pieza | SI53304 | |
| Descripción | 1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL TRANSLATOR | |
| Fabricantes | Silicon Laboratories | |
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Si53304
1:6 LOW JITTER UNIVERSAL BUFFER/LEVEL
TRANSLATOR WITH 2:1 INPUT MUX AND INDIVIDUAL OE
Features
6 differential or 12 LVCMOS outputs Independent VDD and VDDO:
Ultra-low additive jitter: 45 fs rms
1.8/2.5/3.3 V
Wide frequency range: 1 to 725 MHz 1.2/1.5 V LVCMOS output support
Any-format input with pin selectable Excellent power supply noise
output formats: LVPECL, Low Power rejection (PSRR)
LVPECL, LVDS, CML, HCSL,
Selectable LVCMOS drive strength to
LVCMOS
tailor jitter and EMI performance
2:1 mux with hot-swappable inputs Small size: 32-QFN (5x5 mm)
Glitchless input clock switching
RoHS compliant, Pb-free
Synchronous output enable
Industrial temperature range:
Individual output enable
–40 to +85 °C
Applications
High-speed clock distribution
Ethernet switch/router
Optical Transport Network (OTN)
SONET/SDH
PCI Express Gen 1/2/3
Storage
Telecom
Industrial
Servers
Backplane clock distribution
Description
The Si53304 is an ultra low jitter six output differential buffer with pin-selectable
output clock signal format and individual OE. The Si53304 features a 2:1 mux with
glitchless switching, making it ideal for redundant clocking applications. The
Si53304 utilizes Silicon Laboratories' advanced CMOS technology to fanout
clocks from 1 to 725 MHz with guaranteed low additive jitter, low skew, and low
propagation delay variability. The Si53304 features minimal cross-talk and
provides superior supply noise rejection, simplifying low jitter clock distribution in
noisy environments. Independent core and output bank supply pins provide
integrated level translation without the need for external circuitry.
Functional Block Diagram
VREF
Vref
Generator
VDD
Power
Supply
Filtering
VDDOA
SFOUTA[1:0]
OE[2:0]
Ordering Information:
See page 28.
Pin Assignments
Si53304
OE0
SFOUTA[1]
SFOUTA[0]
Q0
Q0
GND
VDD
CLK_SEL
1
2
3
4
5
6
7
8
GND
PAD
24 OE5
23 SFOUTB[1]
22 SFOUTB[0]
21 Q5
20 Q5
19 VDDOB
18 VDDOA
17 VREF
Patents pending
CLK0
/CLK0
CLK1
/CLK1
CLK_SEL
Switching
Logic
BANK A
VDDOB
SFOUTB[1:0]
OE[5:3]
BANK B
Rev. 1.0 4/14
Copyright © 2014 by Silicon Laboratories
Si53304
1 page  
Si53304
Table 4. Output Characteristics (LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol Test Condition
Min
Output DC Common Mode
Voltage
VCOM
VDDOX – 1.595
Single-Ended
Output Swing*
VSE
0.55
*Note: Unused outputs can be left floating. Do not short unused outputs to ground.
Typ
—
0.80
Max
Unit
VDDOX – 1.245 V
1.050
V
Table 5. Output Characteristics (Low Power LVPECL)
(VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C)
Parameter
Symbol
Test Condition
Min
Output DC Common VCOM RL = 100 across Qn and Qn VDDOX – 1.895
Mode Voltage
Single-Ended
Output Swing
VSE RL = 100 across Qn and Qn
0.25
Typ
0.60
Max
Unit
VDDOX – 1.275 V
0.85 V
Table 6. Output Characteristics—CML
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Symbol
VSE
Test Condition
Terminated as shown in Figure 9
(CML termination).
Min
300
Typ Max Unit
400 550
mV
Table 7. Output Characteristics—LVDS
(VDDOX = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 °C)
Parameter
Single-Ended Output
Swing
Output Common
Mode Voltage
(VDDO = 2.5 V or
3.3V)
Output Common
Mode Voltage
(VDDO = 1.8 V)
Symbol
VSE
VCOM1
VCOM2
Test Condition
RL = 100 Ω across QN and QN
VDDOX = 2.38 to 2.63 V, 2.97 to
3.63 V, RL = 100 Ω across QN
and QN
VDDOX = 1.71 to 1.89 V,
RL = 100 Ω across QN
and QN
Min
247
1.10
0.85
Typ Max
— 490
1.25 1.35
0.97 1.25
Unit
mV
V
V
Rev. 1.0
5
5 Page 
Si53304
2. Functional Description
The Si53304 is a low jitter, low skew 1:6 differential buffer with an integrated 2:1 input mux and individual OE
control. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock
select pin control is used to select the active input clock. The selected clock input is routed to two independent
banks of outputs. Each output bank features control pins to select signal format setting and LVCMOS drive
strength. In addition, each clock output has an independent OE pin for individual clock enable/disable.
2.1. Universal, Any-Format Input
The universal input stage enables simple interfacing to a wide variety of clock formats, including LVPECL, low-
power LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various ac- and dc-coupling
options supported by the device. For the best high-speed performance, the use of differential formats is
recommended. For both single-ended and differential input clocks, the fastest possible slew rate is recommended
as low slew rates can increase the noise floor and degrade jitter performance. Though not required, a minimum
slew rate of 0.75 V/ns is recommended for differential formats and 1.0 V/ns for single-ended formats. See “AN766:
Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information.
Table 15. LVPECL, LVCMOS, and LVDS Input Clock Options
1.8 V
2.5/3.3 V
LVPECL
AC-Couple DC-Couple
N/A N/A
Yes Yes
LVCMOS
AC-Couple DC-Couple
No No
No Yes
LVDS
AC-Couple DC-Couple
Yes No
Yes Yes
Table 16. HCSL and CML Input Clock Options
1.8 V
2.5/3.3 V
HCSL
AC-Couple DC-Couple
No No
Yes (3.3 V) Yes (3.3 V)
CML
AC-Couple DC-Couple
Yes No
Yes No
0.1 µF
CLKx
Si533xx
100
/CLKx
0.1 µF
Figure 2. Differential HCSL, LVPECL, Low-Power LVPECL, LVDS, CML AC-Coupled Input
Termination
VDDO= 3.3 V or 2.5 V
CMOS
Driver
Rs
VDD
1 k
VDD
CLKx
50
/CLKx
VTERM = VDD/2
1 k
VREF
Si533xx
Figure 3. LVCMOS DC-Coupled Input Termination
Rev. 1.0
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53304.PDF ] | |
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