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PDF SI53115 Data sheet ( Hoja de datos )
| Número de pieza | SI53115 | |
| Descripción | 15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER | |
| Fabricantes | Silicon Laboratories | |
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Si53115
15-OUTPUT PCIE GEN3 BUFFER/ ZERO DELAY BUFFER
Features
Fifteen 0.7 V low-power, push- Separate VDDIO for outputs
pull HCSL PCIe Gen3 outputs PLL or bypass mode
100 MHz /133 MHz PLL
Spread spectrum tolerable
operation, supports PCIe and
QPI
PLL bandwidth SW SMBUS
programming overrides the latch
1.05 to 3.3 V I/O supply voltage
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
value from HW pin
Low phase jitter (Intel QPI, PCIe
9 selectable SMBUS addresses
Gen 1/2/3/4 common clock
compliant)
SMBus address configurable to
allow multiple buffers in a single
Gen 3 SRNS Compliant
control network 3.3 V supply 100 ps input-to-output delay
voltage operation
Extended Temperature:
–40 to 85 °C
64-pin QFN
Ordering Information:
See page 30.
Pin Assignments
Applications
Server
Storage
Data center
Enterprise switches and routers
Description
The Si53115 is a 15-output, low-power HCSL differential clock buffer that
meets all of the performance requirements of the Intel DB1200ZL
specification. The device is optimized for distributing reference clocks for
Intel® QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/
Gen 4, SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output can be enabled through I2C
for maximum flexibility and power savings. Measuring PCIe clock jitter is
quick and easy with the Silicon Labs PCIe Clock Jitter Tool. Download it
for free at www.silabs.com/pcie-learningcenter.
VDDA 1
GNDA 2
100M_133M 3
HBW_BYPASS_LBW 4
PWRGD / PWRDN 5
GND 6
VDDR 7
CLK_IN 8
CLK_IN 9
SA_0 10
SDA 11
SCL 12
SA_1 13
FBOUT_NC 14
FBOUT_NC 15
GND 16
Si53115
Patents pending
48 VDD_IO
47 GND
46 DIF_9
45 DIF_9
44 DIF_8
43 DIF_8
42 GND
41 VDD
40 DIF_7
39 DIF_7
38 DIF_6
37 DIF_6
36 VDD_IO
35 GND
34 DIF_5
33 DIF_5
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53115
1 page  
Si53115
Table 2. SMBus Characteristics
Parameter
SMBus Input Low Voltage1
SMBus Input High Voltage1
SMBus Output Low Voltage1
Nominal Bus Voltage1
SMBus Sink Current1
SCLK/SDAT Rise Time1
SCLK/SDAT Fall Time1
SMBus Operating Frequency1, 2
Symbol
VILSMB
VIHSMB
VOLSMB
VDDSMB
IPULLUP
tRSMB
tFSMB
fMINSMB
Test Condition
@ IPULLUP
@ VOL
3 V to 5 V +/-10%
(Max VIL – 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL – 0.15)
Minimum Operating Frequency
Notes:
1. Guaranteed by design and characterization.
2. The differential input clock must be running for the SMBus to be active.
Min Max Unit
0.8 V
2.1 VDDSMB V
0.4 V
2.7 5.5 V
4 mA
1000
ns
300 ns
100 kHz
Table 3. Current Consumption
TA = 0–70 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Symbol
Test Condition
Min Typ Max Unit
Operating Current
Power Down Current
IDDVDD
133 MHz, VDD Rail
IDDVDDA 133 MHz, VDDA + VDDR, PLL Mode
IDDVDDIO 133 MHz, CL = Full Load, VDD IO Rail
IDDVDDPD
Power Down, VDD Rail
IDDVDDAPD
Power Down, VDDA Rail
IDDVDDIOPD
Power Down, VDD_IO Rail
—
—
—
—
—
—
25 30 mA
20 25 mA
100 110 mA
0.5 1 mA
4 7 mA
0.4 0.7 mA
Rev. 1.1
5
5 Page 
Si53115
Table 7. DIF 0.7 V AC Timing Characteristics (Non-Spread Spectrum Mode)1 (Continued)
Parameter
Symbol
CLK 100 MHz, 133 MHz
Unit
Maximum Voltage (Undershoot) 3,8,20
Ringback Voltage
Vuds
Vrb
Min Typ
Max
— — VLow – 0.3 V
0.2 — N/A V
Notes:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. This is the time from the valid CLK_IN input clocks and the assertion of the PWRGD signal level at 1.8–2.0 V to the
time that stable clocks are output from the buffer chip (PLL locked).
3. Test configuration is Rs = 33.2 , 2 pF for 100 transmission line; Rs = 27 , 2 pF for 85 transmission line.
4. Measurement taken from differential waveform.
5. Using frequency counter with the measurement interval equal or greater than 0.15 s, target frequencies are
99,750,00 Hz, 133,000,000 Hz.
6. The average period over any 1 µs period of time must be greater than the minimum and less than the maximum
specified period.
7. Measure taken from differential waveform on a component test board. The edge (slew) rate is measured from
–150 mV to +150 mV on the differential waveform. Scope is set to average because the scope sample clock is making
most of the dynamic wiggles along the clock edge. Only valid for Rising clock and Falling CLOCK. Signal must be
monotonic through the Vol to Voh region for Trise and Tfall.
8. Measurement taken from single-ended waveform.
9. Measured with oscilloscope, averaging off, using min max statistics. Variation is the delta between min and max.
10. Measured with oscilloscope, and averaging on. The difference between the rising edge rate (average) of clock verses
the falling edge rate (average) of CLOCK.
11. Rise/Fall matching is derived using the following, 2*(Trise – Tfall) / (Trise + Tfall).
12. VHigh is defined as the statistical average High value as obtained by using the Oscilloscope VHigh Math function.
13. VLow is defined as the statistical average Low value as obtained by using the Oscilloscope VLow Math function.
14. Measured at crossing point where the instantaneous voltage value of the rising edge of CLK equals the falling edge of
CLK.
15. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge
is crossing.
16. The crossing point must meet the absolute and relative crossing point specifications simultaneously.
17. Vcross(rel) Min and Max are derived using the following, Vcross(rel) Min = 0.250 + 0.5 (Vhavg – 0.700), Vcross(rel)
Max = 0.550 – 0.5 (0.700 – Vhavg), (see Figure 3–4 for further clarification).
18. Vcross is defined as the total variation of all crossing voltages of Rising CLOCK and Falling CLOCK. This is the
maximum allowed variance in Vcross for any particular system.
19. Overshoot is defined as the absolute value of the maximum voltage.
20. Undershoot is defined as the absolute value of the minimum voltage.
Rev. 1.1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53115.PDF ] | |
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