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PDF SI53112 Data sheet ( Hoja de datos )
| Número de pieza | SI53112 | |
| Descripción | DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER | |
| Fabricantes | Silicon Laboratories | |
| Logotipo |  |
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Si53112
DB1200ZL 12-OUTPUT PCIE GEN 3 BUFFER
Features
Twelve 0.7 V low-power, push- PLL or bypass mode
pull, HCSL-compatible
Spread spectrum tolerable
PCIe Gen 3 outputs
1.05 to 3.3 V I/O supply voltage
Individual OE HW pins for each
output clock
100 MHz /133 MHz PLL
operation, supports PCIe and
QPI
50 ps output-to-output skew
50 ps cyc-cyc jitter (PLL mode)
Low phase jitter (Intel QPI, PCIe
Gen 1/2/3/4 common clock
compliant)
PLL bandwidth SW SMBUS
programming overrides the latch
Gen 3 SRNS Compliant
value from HW pin
100 ps input-to-output delay
9 selectable SMBUS addresses
SMBus address configurable to
allow multiple buffers in a single
Extended Temperature:
–40 to 85 °C
Package: 64-pin QFN
control network 3.3 V supply For higher output devices or
voltage operation
variations of this device, contact
Silicon Labs
Ordering Information:
See page 30.
Patents pending
Applications
Server
Storage
Datacenter
Enterprise Switches and Routers
Description
The Si53112 is a low-power, 12-output, differential clock buffer that meets
all of the performance requirements of the Intel DB1200ZL specification.
The device is optimized for distributing reference clocks for Intel®
QuickPath Interconnect (Intel QPI), PCIe Gen 1/Gen 2/Gen 3/Gen 4,
SAS, SATA, and Intel Scalable Memory Interconnect (Intel SMI)
applications. The VCO of the device is optimized to support 100 MHz and
133 MHz operation. Each differential output has a dedicated hardware
output enable pin for maximum flexibility and power savings. Measuring
PCIe clock jitter is quick and easy with the Silicon Labs PCIe Clock Jitter
Tool. Download it for free at www.silabs.com/pcie-learningcenter.
Rev. 1.1 12/15
Copyright © 2015 by Silicon Laboratories
Si53112
1 page  
Si53112
Table 3. Output Skew, PLL Bandwidth and Peaking
TA = –40 to 85 °C; supply voltage VDD = 3.3 V ±5%
Parameter
Test Condition
Min TYP Max Unit
CLK_IN, DIF[x:0]
Input-to-Output Delay in PLL Mode
Nominal Value1,2,3,4
–100
27
100
ps
CLK_IN, DIF[x:0]
Input-to-Output Delay in Bypass Mode
\Nominal Value2,4,5
2.5 3.3 4.5 ns
CLK_IN, DIF[x:0]
Input-to-Output Delay Variation in PLL mode
Over voltage and temperature2,4,5
–100
39
100
ps
CLK_IN, DIF[x:0] Input-to-Output Delay Variation in Bypass Mode –250
3.7
250
ps
Over voltage and temperature2,4,5
DIF[11:0]
PLL Jitter Peaking
Output-to-Output Skew across all 12 Outputs
(Common to Bypass and PLL Mode)1,2,3,4,5
(HBW_BYPASS_LBW = 0)6
0 20 50 ps
— 0.4 2.0 dB
PLL Jitter Peaking (HBW_BYPASS_LBW = 1)6
— 0.1 2.5 dB
PLL Bandwidth
(HBW_BYPASS_LBW = 0)7
— 0.7 1.4 MHz
PLL Bandwidth
(HBW_BYPASS_LBW = 1)7
— 2 4 MHz
Notes:
1. Measured into fixed 2 pF load cap. Input-to-output skew is measured at the first output edge following the
corresponding input.
2. Measured from differential cross-point to differential cross-point.
3. This parameter is deterministic for a given device.
4. Measured with scope averaging on to find mean value.
5. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created
by it.
6. Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL
jitter peaking.
7. Measured at 3 db down or half power point.
Rev. 1.1
5
5 Page 
Si53112
2. Functional Description
2.1. CLK_IN, CLK_IN
The differential input clock is expected to be sourced from a clock synthesizer, e.g. CK420BQ, CK509B, or CK410B+.
2.2. OE and Output Enables (Control Registers)
Each output can be individually enabled or disabled by SMBus control register bits. Additionally, each output of the
DIF[11:0] has a dedicated OE pin. The OE pins are asynchronous, asserted-low signals. The Output Enable bits in
the SMBus registers are active high and are set to enable by default. The disabled state for the DB1200ZL NMOS
push-pull output is Low/Low. Please note that the logic level for assertion or deassertion is different in software
than it is on hardware. This follows hardware default nomenclature for communication channels (e.g., output is
enabled if the OE# pin is pulled low) and still maintains software programming logic (e.g., output is enabled if OE
register is true). Table 9 is a truth table depicting enabling and disabling of outputs via hardware and software. Note
that, for the output to be active, the control register bit must be a 1 and the OE pin must be a 0.
Note: The assertion and deassertion of this signal is absolutely asynchronous.
Table 9. Si53112 Output Management
Inputs
PWRGD/
PWRDN
CLK_IN/
CLK_IN
0x
1 Running
OE Hardware Pins and Control Register Bits
SMBUS
Enable Bit
OE Pin DIF/DIF[11:0]
x x Low/Low
0 x Low/Low
1 0 Running
1 1 Low/Low
Outputs
FB_OUT/
FB_OUT
Low/Low
Running
Running
Running
PLL State
OFF
ON
ON
ON
2.2.1. OE Assertion (Transition from 1 to 0)
All differential outputs that were disabled are to resume normal operation in a glitch-free manner. The latency from
the assertion to active outputs is 4 to 12 DIF clock periods.
2.2.2. OE De-Assertion (Transition from 0 to 1)
The impact of deasserting OE is that each corresponding output will transition from normal operation to disabled in
a glitch-free manner. A minimum of four valid clocks will be provided after the deassertion of OE. The maximum
latency from the deassertion to disabled outputs is 12 DIF clock periods.
2.3. 100M_133M—Frequency Selection
The Si53112 is optimized for lowest phase jitter performance at operating frequencies of 100 and 133 MHz.
100M_133M is a hardware input pin, which programs the appropriate output frequency of the differential outputs.
Note that the CLK_IN frequency must be equal to the CLK_OUT frequency; meaning Si53112 is operated in 1:1
mode only. Frequency selection can be enabled by the 100M_133M hardware pin. An external pull-up or pull-down
resistor is attached to this pin to select the input/output frequency. The functionality is summarized in Table 10.
Table 10. Frequency Program Table
100M_133M
0
1
Optimized Frequency (CLK_IN = CLK_OUT)
133.33 MHz
100.00 MHz
Note: All differential outputs transition from 100 to 133 MHz or from 133 to 100 MHz in a glitch free manner.
Rev. 1.1
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SI53112.PDF ] | |
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