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PDF LTC3300-2 Data sheet ( Hoja de datos )
| Número de pieza | LTC3300-2 | |
| Descripción | Addressable High Efficiency Bidirectional Multicell Battery Balancer | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n Bidirectional Synchronous Flyback Balancing
of Up to 6 Li-Ion or LiFePO4 Cells in Series
n Up to 10A Balancing Current (Set by Externals)
n Integrates Seamlessly with the LTC680x Family of
Multicell Battery Stack Monitors
n Bidirectional Architecture Minimizes Balancing
Time and Power Dissipation
n Up to 92% Charge Transfer Efficiency
n Stackable Architecture Enables >800V Systems
n Uses Simple 2-Winding Transformers
n 1MHz Serial Interface with 4-Bit
CRC Packet Error Checking
n Individually Addressable with 5-Bit Address
n Numerous Fault Protection Features
n 48-Lead Exposed Pad QFN and LQFP Packages
APPLICATIONS
n Electric Vehicles/Plug-in HEVs
n High Power UPS/Grid Energy Storage Systems
n General Purpose Multicell Battery Stacks
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and isoSPI
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
LTC3300-2
Addressable High Efficiency
Bidirectional Multicell
Battery Balancer
DESCRIPTION
The LTC®3300-2 is a fault-protected controller IC for
transformer-based bidirectional active balancing of multi-
cell battery stacks. All associated gate drive circuitry,
precision current sensing, fault detection circuitry and a
robust serial interface with built-in watchdog timer are
integrated.
Each LTC3300-2 can balance up to 6 series-connected
battery cells with an input common mode voltage up to
36V. Charge from any selected cell can be transferred at
high efficiency to or from 12 or more adjacent cells. Each
LTC3300-2 has an individually addressable serial interface,
allowing up to 32 LTC3300-2 devices to interface to one
control processor.
Fault protection features include readback capability, cy-
clic redundancy check (CRC) error detection, maximum
on-time volt-second clamps, and overvoltage shutoffs.
The related LTC3300-1 offers a serial interface that allows
the serial ports of multiple LTC3300-1 devices to be daisy-
chained without opto-couplers or isolators.
TYPICAL APPLICATION
High Efficiency Bidirectional Balancing
NEXT CELL ABOVE
CHARGE
SUPPLY
(ICHARGE 1-6)
CHARGE
RETURN
(IDISCHARGE 1-6)
+
CELL 12
LTC3300-2
4
ISOLATOR
+ CELL 7 ADDRESS n + 1
5
CHARGE
RETURN
•
+IDISCHARGE
CELL 6
•
•
CHARGE
SUPPLY
ICHARGE
•
+
CELL 1
NEXT CELL BELOW
LTC3300-2
4
ADDRESS n
5
33002 TA01a
ISOLATOR
4
4
SERIAL I/O
4
Balancer Efficiency
100
DC2064A DEMO BOARD
ICHARGE = IDISCHARGE = 2.5A
VCELL = 3.6V
95
CHARGE
90 DISCHARGE
85
80
6 8 10 12
NUMBER OF CELLS (SECONDARY SIDE)
33001 TA01b
For more information www.linear.com/LTC3300-2
33002f
1
1 page  
LTC3300-2
E LECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the specified operating
junction temperature range,
C3 = 10.8V, C2 = 7.2V, C1 =
otherwise
3.6V, V– =
s0pVe,cuifnilceastsioontshearrewiasteTnAo=te2d5.°C.
(Note
2)
BOOST+
=
25.2V,
C6
=
21.6V,
C5
=
18V,
C4
=
14.4V,
SYMBOL
t5
t6
t7
t8
fCLK
tWD1
PARAMETER
CSBI Pulse Width
SCKI Rising to CSBI Rising
CSBI Falling to SCKI Rising
SCKI Falling to SDO Valid
Clock Frequency
Watchdog Timer Timeout Period
tWD2 Watchdog Timer Reset Time
Digital I/O Specifications
VIH Digital Input Voltage High
VIL Digital Input Voltage Low
IIH Digital Input Current High
IIL Digital Input Current Low
VOL Digital Output Voltage Low
IOH Digital Output Current High
CONDITIONS
Read Operation
WDT Assertion Measured from Last Valid
Command Byte
WDT Negation Measured from Last Valid
Command Byte
Pins CSBI, SCKI, SDI
Pins CTRL, BOOST
Pins A4, A3, A2, A1, A0
Pin WDT
Pins CSBI, SCKI, SDI
Pins CTRL, BOOST
Pins A4, A3, A2, A1, A0
Pin WDT
Pins CSBI, SCKI, SDI
Pins CTRL, BOOST
Pins A4, A3, A2, A1, A0
Pin WDT, Timed Out
Pins CSBI, SCKI, SDI
Pins CTRL, BOOST
Pins A4, A3, A2, A1, A0
Pin WDT, Not Balancing
Pin SDO, Sinking 500µA; Read
Pin SDO at 6V
MIN
l 400
l 100
l 100
l
l
l 0.75
l
TYP MAX UNITS
ns
ns
ns
250 ns
1 MHz
1.5 2.25 second
1.5 5
µs
l VREG – 0.5
l
l
l
VVRREEGG2––
0.5
0.5
l
l
l
l
–1
–1
–1
–1
–1
–1
–1
–1
l
l
0
0
0
0
0
0
0
0
0.5
0.5
0.5
0.8
1
1
1
1
1
1
1
1
0.3
100
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
V
nA
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3300-2 is tested under pulsed load conditions such
that TJ ≈ TA. The LTC3300I-2 is guaranteed over the –40°C to 125°C
operating junction temperature range and the LTC3300H-2 is guaranteed
over the –40°C to 150°C operating junction temperature. High junction
temperatures degrade operating lifetimes; operating lifetime is derated
for junction temperatures greater than 125°C. Note that the maximum
ambient temperature consistent with these specifications is determined by
specific operating conditions in conjunction with board layout, the rated
package thermal impedance and other environmental factors. The junction
temperature (TJ, in °C) is calculated from the ambient temperature
(TA, in °C) and power dissipation (PD, in Watts) according to the formula:
TJ = TA + (PD • θJA)
where θJA (in °C/W) is the package thermal impedance.
Note 3: When balancing more than one cell at a time, the individual cell
supply currents can be calculated from the values given in the table as
follows: First add the appropriate table entries cell by cell for the balancers
that are on. Second, for each additional balancer that is on, subtract 70µA
from the resultant sums for C1, C2, C3, C4, and C5, and 450µA from the
resultant sum for C6. For example, if all six balancers are on, the resultant
current for C1 is [250 – 70 + 70 + 70 + 70 + 70 – 5(70)]µA = 110µA and
for C6 is [560 + 560 + 560 + 560 + 560 + 740 – 5(450)]µA = 1290µA.
Note 4: Dynamic supply current is higher due to gate charge being
delivered at the switching frequency during active balancing. See Gate
Drivers/Gate Drive Comparators and Voltage Regulator in the Operation
section for more information on estimating these currents.
Note 5: The zero current sense voltages given in the table are DC
thresholds. The actual zero current sense voltage seen in application will
be closer to zero due to the slew rate of the winding current and the finite
delay of the current sense comparator.
Note 6: The mid-range value is the average of the minimum and maximum
readings within the group of six.
Note 7: This IC includes overtemperature protection intended to protect
the device during momentary overload conditions. The maximum junction
temperature may be exceeded when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may result in device degradation or failure.
For more information www.linear.com/LTC3300-2
33002f
5
5 Page 
BLOCK DIAGRAM
LTC3300-2
C6
VOLTAGE
REGULATOR
48
VREG
40mA
MAX
4.8V
V– POR
THERMAL
SHUTDOWN
47 A4
46 A3
45 A2
44 A1
43 A0
5
ADDRESS
LEVEL-SHIFTING
SERIAL
INTERFACE
16
DATA
12
STATUS
12
19 SDO
18 SDI
17 SCKI
16 CSBI
WDT
20
5.6V
V–
1.2V
RTONS
V–
21
RESET
EXPOSED
PAD
49
WATCHDOG
TIMER
ACTIVE
V–
41
BOOST–
C6
40
BOOST+
SD
2
VREG
BOOST
GATE DRIVE
GENERATOR
BOOST+
BOOST 42
C6 39
G6P 38
C5 + C5
– 50mV/0
I6P 37
0/50mV
VREG
I6S 2
G6S 1
V–
6-CELL
SYNCHRONOUS
FLYBACK
CONTROLLER
BALANCER
PINS 3 TO 10,
25 TO 36
C1 24
C2
G1P 23
V– + I1P 22
2 – 50mV/0
0/50mV
VREG
I1S 12
G1S 11
V–
MAX ON-TIME
VOLT-SEC
CLAMPS
CTRL V– RTONS
15 13
RTONP
14
33002 BD
For more information www.linear.com/LTC3300-2
33002f
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3300-2.PDF ] | |
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