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PDF LTC3300-1 Data sheet ( Hoja de datos )
| Número de pieza | LTC3300-1 | |
| Descripción | High Efficiency Bidirectional Multicell Battery Balancer | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n Bidirectional Synchronous Flyback Balancing
of Up to 6 Li-Ion or LiFePO4 Cells in Series
n Up to 10A Balancing Current (Set by Externals)
n Integrates Seamlessly with the LTC680x Family of
Multicell Battery Stack Monitors
n Bidirectional Architecture Minimizes Balancing
Time and Power Dissipation
n Up to 92% Charge Transfer Efficiency
n Stackable Architecture Enables >1000V Systems
n Uses Simple 2-Winding Transformers
n 1MHz Daisy-Chainable Serial Interface with 4-Bit
CRC Packet Error Checking
n High Noise Margin Serial Communication
n Numerous Fault Protection Features
n 48-Lead Exposed Pad QFN and LQFP Packages
APPLICATIONS
n Electric Vehicles/Plug-in HEVs
n High Power UPS/Grid Energy Storage Systems
n General Purpose Multicell Battery Stacks
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and isoSPI
is a trademark of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
LTC3300-1
High Efficiency Bidirectional
Multicell Battery Balancer
DESCRIPTION
The LTC®3300-1 is a fault-protected controller IC for
transformer-based bidirectional active balancing of multi-
cell battery stacks. All associated gate drive circuitry,
precision current sensing, fault detection circuitry and a
robust serial interface with built-in watchdog timer are
integrated.
Each LTC3300-1 can balance up to 6 series-connected bat-
tery cells with an input common mode voltage up to 36V.
Charge from any selected cell can be transferred at high
efficiency to or from 12 or more adjacent cells. A unique
level-shifting SPI-compatible serial interface enables
multiple LTC3300-1 devices to be connected in series,
without opto-couplers or isolators, allowing for balancing
of every cell in a long string of series-connected batteries.
When multiple LTC3300-1 devices are connected in series
they can operate simultaneously, permitting all cells in
the stack to be balanced concurrently and independently.
Fault protection features include readback capability, cy-
clic redundancy check (CRC) error detection, maximum
on-time volt-second clamps, and overvoltage shutoffs.
TYPICAL APPLICATION
High Efficiency Bidirectional Balancing
NEXT CELL ABOVE
CHARGE
SUPPLY
(ICHARGE 1-6)
CHARGE
RETURN
(IDISCHARGE 1-6)
+
CELL 12
CHARGE
RETURN
+
+•
IDISCHARGE
•
CELL 7
CELL 6
LTC3300-1
3
SERIAL
DATA OUT
TO LTC3300-1
ABOVE
3
3
•
CHARGE
SUPPLY
ICHARGE
•
+
CELL 1
LTC3300-1
SERIAL
3 DATA IN
FROM
LTC3300-1
BELOW
NEXT CELL BELOW
33001 TA01a
Balancer Efficiency
100
DC2064A DEMO BOARD
ICHARGE = IDISCHARGE = 2.5A
VCELL = 3.6V
95
CHARGE
90 DISCHARGE
85
80
6 8 10 12
NUMBER OF CELLS (SECONDARY SIDE)
33001 TA01b
For more information www.linear.com/LTC3300-1
33001fb
1
1 page  
LTC3300-1
E LECTRICAL CHAR ACTERISTICS The l denotes the specifications which apply over the full operating
Cju3nc=ti1o0n.8teV,mCp2er=a7tu.r2eV,raCn1g=e,3o.6thV,erVw–i=se0sV,peucnilfeicsastoiothnesrawrieseatnToAte=d.25°C. (Note 2) BOOST+ = 25.2V, C6 = 21.6V, C5 = 18V, C4 = 14.4V,
SYMBOL
PARAMETER
CONDITIONS
MIN TYP MAX UNITS
tr_S
tf_S
tONP|MAX
Secondary Winding Gate Drive
Rise Time (10% to 90%)
Secondary Winding Gate Drive Fall
Time (90% to 10%)
Primary Winding Switch Maximum
On-Time
G1S, CGATE = 2500pF
G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF
G1S, CGATE = 2500pF
G2S Through G6S, CTRL = 0 Only, CGATE = 2500pF
RRTONP = 20kΩ (Measured at G1P-G6P)
l
6
30 60
30 60
20 40
20 40
7.2 8.4
ns
ns
ns
ns
µs
tONS|MAX
tONP|MAX Matching (All 6)
Secondary Winding Switch
Maximum On-Time
±[(Max – Min)/(Max + Min)] • 100%
RRTONS = 15kΩ (Measured at G1S-G6S)
l
l1
±1 ±4
1.2 1.4
%
µs
tDLY_START
tONS|MAX Matching (All 6)
Delayed Start Time After New/
Different Balance Command or
Recovery from Voltage/Temp Fault
±[(Max – Min)/(Max + Min)] • 100%
l
±1 ±4
2
%
ms
Voltage Mode Timing Specifications
t1 SDI Valid to SCKI Rising Setup Write Operation
l 10
ns
t2 SDI Valid from SCKI Rising Hold Write Operation
l 250
ns
t3 SCKI Low
l 400
ns
t4 SCKI High
l 400
ns
t5 CSBI Pulse Width
l 400
ns
t6 SCKI Rising to CSBI Rising
l 100
ns
t7 CSBI Falling to SCKI Rising
l 100
ns
t8
SCKI Falling to SDO Valid
Read Operation
l 250 ns
fCLK Clock Frequency
l 1 MHz
tWD1
Watchdog Timer Timeout Period WDT Assertion Measured from Last Valid
Command Byte
l 0.75
1.5 2.25 second
tWD2
Watchdog Timer Reset Time
WDT Negation Measured from Last Valid
Command Byte
l
1.5 5
µs
Current Mode Timing Specifications
tPD1 CSBI to CSBO Delay
tPD2 SCKI Rising to SCKO Delay
tPD3 SDI to SDOI Delay
tPD4 SCKI Falling to SDOI Valid
tPD5 SCKI Falling to SDI Valid
tSCKO
SCKO Pulse Width
Voltage Mode Digital I/O Specifications
CCSBO = 150pF
CSCKO = 150pF
CSDOI = 150pF, Command Byte
CSDOI = 150pF, Write Balance Command
CSDI = 150pF, Read Operation
CSCKO = 150pF
l
l
l
l
l
600
300
300
300
300
100
ns
ns
ns
ns
ns
ns
VIH
Digital Input Voltage High
Pins CSBI, SCKI, SDI; VMODE = VREG
Pins CTRL, BOOST, VMODE, TOS
Pin WDT
l VREG – 0.5
l VREG – 0.5
l2
V
V
V
VIL
Digital Input Voltage Low
Pins CSBI, SCKI, SDI; VMODE = VREG
Pins CTRL, BOOST, VMODE, TOS
Pin WDT
l
l
l
0.5 V
0.5 V
0.8 V
IIH
Digital Input Current High
Pins CSBI, SCKI, SDI; VMODE = VREG
PPiinnsWCDTTR,LT,imBOedOSOTu,tVMODE, TOS
–1 0 1
–1 0 1
–1 0 1
µA
µA
µA
IIL
Digital Input Current Low
Pins CSBI, SCKI, SDI; VMODE = VREG
PPiinnsWCDTTR,LN,oBtOBOaSlaTn,cVinMgODE, TOS
–1 0 1
–1 0 1
–1 0 1
µA
µA
µA
For more information www.linear.com/LTC3300-1
33001fb
5
5 Page 
LTC3300-1
PIN FUNCTIONS
G1P, G2P, G3P, G4P, G5P, G6P (Pins 23, 26, 29, 32, 35,
38): G1P through G6P are gate driver outputs for driving
external NMOS transistors connected in series with the
primary windings of transformers connected in parallel
with battery cells 1 through 6.
C1, C2, C3, C4, C5, C6 (Pins 24, 27, 30, 33, 36, 39):
C1 through C6 connect to the positive terminals of bat-
tery cells 1 through 6. Connect the negative terminal of
battery cell 1 to V–.
BOOST+ (Pin 40): Boost+ Pin. Connects to the anode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. A Schottky diode from C6
to BOOST+ is needed as well. Alternately, the BOOST+ pin
can connect to one cell up in the above sub-stack (if pres-
ent). This pin is effectively C7. (Note: “Sub-stack” refers
to the 3-6 battery cells connected locally to an individual
LTC3300-1 as part of a larger stack.)
BOOST– (Pin 41): Boost– Pin. Connects to the cathode of
the external flying capacitor used for generating sufficient
gate drive necessary for balancing the topmost battery cell
in a given LTC3300-1 sub-stack. Alternately, if the BOOST+
pin connects to the next higher cell in the above sub-stack
(if present), this pin is a no connect.
BOOST (Pin 42): Enable Boost Pin. Connect BOOST to VREG
to enable the boosted gate drive needed for balancing the
top cell in a given LTC3300-1 sub-stack. If the BOOST+ pin
can be connected to the next cell up in the stack (i.e., C1
of the next LTC3300-1 in the stack), then BOOST should
be tied to V– and BOOST– no connected. This pin must
be tied to either VREG or V–.
SDOI (Pin 43): Serial Data Output/Input. SDOI transfers
data to and from the next IC higher in the daisy chain when
writing and reading. See Serial Port in the Applications
Information section.
SCKO (Pin 44): Serial Clock Output. SCKO is a buffered
and one-shotted version of the serial clock input, SCKI,
when CSBI is low. SCKO drives the next IC higher in the
daisy chain. See Serial Port in the Applications Informa-
tion section.
CSBO (Pin 45): Chip Select (Active Low) Output. CSBO
is a buffered version of the chip select input, CSBI. CSBO
drives the next IC higher in the daisy chain. See Serial Port
in the Applications Information section.
VMODE (Pin 46): Voltage Mode Input. When VMODE is tied
to VREG, the CSBI, SCKI, SDI and SDO pins are configured
as voltage inputs and outputs. This means these pins
accept VREG-referred rail-to-rail logic levels. Connect
VMODE to VREG when the LTC3300-1 is the bottom device
in a daisy chain.
When VMODE is tied to V–, the CSBI, SCKI and SDI pins
are configured as current inputs and outputs, and SDO is
unused. Connect VMODE to V– when the LTC3300-1 is be-
ing driven by another LTC3300-1 lower in the daisy chain.
This pin must be tied to either VREG or V–.
TOS (Pin 47): Top Of Stack Input. Tie TOS to VREG when
the LTC3300-1 is the top device in a daisy chain. Tie TOS
to V– when the LTC3300-1 is any other device in the daisy
chain. When TOS is tied to VREG, the
the SDOI input. When TOS is tied to
LTC3300-1 ignores
V–, the LTC3300-1
expects data to be passed to and from the SDOI pin. This
pin must be tied to either VREG or V–.
VREG (Pin 48): Linear Voltage Regulator Output. This 4.8V
output should be bypassed with a 1µF or larger capacitor
to V–. The VREG pin is capable of supplying up to 40mA
to internal and external loads. The VREG pin does not sink
current.
V– (Exposed Pad Pin 49): The exposed pad should be
connected to a continuous (ground) plane biased at V– on
the second layer of the printed circuit board by several
vias directly under the LTC3300-1.
For more information www.linear.com/LTC3300-1
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11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LTC3300-1.PDF ] | |
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