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PDF ASM2I9940L Data sheet ( Hoja de datos )
| Número de pieza | ASM2I9940L | |
| Descripción | Low Voltage 1:18 Clock Distribution Chip | |
| Fabricantes | Alliance Semiconductor | |
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June 2005
ASM2I9940L
rev 1.0
Low Voltage 1:18 Clock Distribution Chip
Features
LVPECL or LVCMOS Clock Input
2.5V LVCMOS Outputs for Pentium II
Microprocessor Support*
150pS Maximum Output-to-Output Skew
Maximum Output Frequency of 250MHz
32 Lead LQFP & TQFP Packaging
Dual or Single Supply Device:
Dual VCC Supply Voltage, 3.3V Core and
2.5V Output
Single 3.3V VCC Supply Voltage for 3.3V
Outputs
Single 2.5V VCC Supply Voltage for 2.5V I/O
Pin and Function compatible to MPC940L,
MPC9109, CY29940 and CY29940-1
Functional Description
The ASM2I9940L is a 1:18 low Voltage Clock distribution
chip with 2.5V or 3.3V LVCMOS output capabilities. The
device features the capability to select either a differential
LVPECL or LVCMOS compatible input. The 18 outputs are
2.5V or 3.3V LVCMOS compatible and feature the drive
strength to drive 50Ω series or parallel terminated
transmission lines. With output-to-output skews of 150pS,
the ASM2I9940L is ideal as a clock distribution chip for the
most demanding of Synchronous systems. The 2.5V
outputs also make the device ideal for supplying clocks for
a high performance microprocessor based design.
With low output impedance (≈20Ω), in both the HIGH and
LOW logic states, the output buffers of the ASM2I9940L
are ideal for driving series terminated transmission lines.
With a 20Ω output impedance the ASM2I9940L has the
capability of driving two series terminated lines from each
output. This gives the device an effective fanout of 1:36.
The differential LVPECL inputs of the ASM2I9940L allow
the device to interface directly with a LVPECL fanout buffer
to build very wide clock fanout trees or to couple to a high
frequency clock source. The LVCMOS input provides a
more standard interface for applications requiring only a
single clock distribution chip at relatively low frequencies. In
addition, the two clock sources can be used to provide for a
test clock interface as well as the primary system clock. A
logic HIGH on the LVCMOS_CLK_Sel pin will select the
LVCMOS level clock input. All inputs of the ASM2I9940L
have internal pullup/pulldown resistor, so they can be left
open if unused.
The ASM2I9940L is a single or dual supply device. The
device power supply offers a high degree of flexibility. The
device can operate with a 3.3V core and 3.3V output, a
3.3V core and 2.5V outputs as well as a 2.5V core and
2.5V outputs. The 32-lead LQFP and TQFP Packages
were chosen to optimize performance, board space and
cost of the device. The 32-lead LQFP and TQFP Packages
have a 7x7mm2 body size with conservative 0.8mm pin
spacing.
* Pentium II is a trademark of Intel Corporation
Alliance Semiconductor
2575, Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
1 page  
June 2005
ASM2I9940L
rev 1.0
Table 7. DC Characteristics (TA = 0° to 70°C, VCCI = 3.3V ± 5%, VCCO = 2.5V ± 5%)
Symbol
VIH
VIL
VPP
VCMR
VOH
VOL
IIN
CIN
Cpd
ZOUT
ICC
Characteristic
Input HIGH Voltage
CMOS_CLK
Input LOW Voltage
CMOS_CLK
Peak–to–Peak Input
Voltage
PECL_CLK
Common Mode Range
PECL_CLK
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
Min
2.4
500
VCC–1.4
1.8
Typ
4.0
10
23
0.5
Max
VCCI
0.8
1000
VCC–0.6
0.5
±200
1.0
Table 8. AC Characteristics (TA = 0° to 70°C, VCCI = 3.3V ± 5%, VCCO = 2.5V ± 5% )
Symbol
Fmax
tPLH
tPLH
tsk(o)
Characteristic
Maximum Input Frequency
Propagation Delay
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
Propagation Delay
Output-to-output Skew
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
PECL_CLK
CMOS_CLK
Min
2.0
1.7
2.0
1.8
Typ
2.8
2.5
2.9
2.5
Max
250
3.5
3.0
3.8
3.3
150
150
tsk(pp)
tsk(pp)
Part–to–Part Skew
Part–to–Part Skew
PECL_CLK < 150MHz
CMOS_CLK < 150MHz
PECL_CLK > 150MHz
CMOS_CLK > 150MHz
tsk(pp)
Part–to–Part Skew
PECL_CLK CMOS_CLK
DC Output Duty Cycle
fCLK < 134 MHz
fCLK <250 MHz
tr, tf Output Rise/Fall Time
Note: 1.Tested using standard input levels, Production tested @ 150MHz.
2. Across temperature and voltage ranges, includes output skew.
3. For a specific temperature and voltage, includes output skew.
45
40
0.3
50
50
1.5
1.3
1.8
1.5
850
750
55
60
1.2
Unit
V
V
mV
V
V
V
µA
pF
pF
Ω
mA
Unit
MHz
nS
nS
pS
nS
nS
pS
%
%
nS
Condition
IOH = –20mA
IOH = 20mA
per output
Condition
Note1.
Note1
Notes1,2
Notes1,2
Notes1,3
Input DC = 50%
Input DC = 50%
0.5 – 1.8 V
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
5 of 13
5 Page 
June 2005
rev 1.0
32-lead LQFP Package
ASM2I9940L
SECTION A-A
Symbol
A
A1
A2
D
D1
E
E1
L
L1
T
T1
b
b1
R0
e
a
Dimensions
Inches
Millimeters
Min Max Min Max
….
0.0630
…
1.6
0.0020
0.0059
0.05
0.15
0.0531
0.0571
1.35
1.45
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.3465
0.3622
8.8
9.2
0.2717
0.2795
6.9
7.1
0.0177
0.0295
0.45
0.75
0.03937 REF
1.00 REF
0.0035
0.0079
0.09
0.2
0.0038
0.0062
0.097
0.157
0.0118
0.0177
0.30
0.45
0.0118
0.0157
0.30
0.40
0.0031
0.0079
0.08
0.20
0.031 BASE
0.8 BASE
0° 7° 0° 7°
Low Voltage 1:18 Clock Distribution Chip
Notice: The information in this document is subject to change without notice.
11 of 13
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