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PDF ASM2I9940L Data sheet ( Hoja de datos )
| Número de pieza | ASM2I9940L | |
| Descripción | Low Voltage 1:18 Clock Distribution Chip | |
| Fabricantes | ON Semiconductor | |
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ASM2I9940L
Low Voltage 1:18 Clock
Distribution Chip
Functional Description
The ASM2I9940L is a 1:18 low Voltage Clock distribution chip
with 2.5 V or 3.3 V LVCMOS output capabilities. The device features
the capability to select either a differential LVPECL or LVCMOS
compatible input. The 18 outputs are 2.5 V or 3.3 V LVCMOS
compatible and feature the drive strength to drive 50 W series or
parallel terminated transmission lines. With output−to−output skews
of 150 pS, the ASM2I9940L is ideal as a clock distribution chip for the
most demanding of Synchronous systems. The 2.5 V outputs also
make the device ideal for supplying clocks for a high performance
microprocessor based design.
With low output impedance (≈20 W), in both the HIGH and LOW
logic states, the output buffers of the ASM2I9940L are ideal for
driving series terminated transmission lines. With a 20 W output
impedance the ASM2I9940L has the capability of driving two series
terminated lines from each output. This gives the device an effective
fanout of 1:36.
The differential LVPECL inputs of the ASM2I9940L allow the
device to interface directly with a LVPECL fanout buffer to build very
wide clock fanout trees or to couple to a high frequency clock source.
The LVCMOS input provides a more standard interface for
applications requiring only a single clock distribution chip at
relatively low frequencies. In addition, the two clock sources can be
used to provide for a test clock interface as well as the primary system
clock. A logic HIGH on the LVCMOS_CLK_Sel pin will select the
LVCMOS level clock input. All inputs of the ASM2I9940L have
internal pullup/pulldown resistor, so they can be left open if unused.
The ASM2I9940L is a single or dual supply device. The device
power supply offers a high degree of flexibility. The device can
operate with a 3.3 V core and 3.3 V output, a 3.3 V core and 2.5 V
outputs as well as a 2.5 V core and 2.5 V outputs. The 32−lead LQFP
Package was chosen to optimize performance, board space and cost of
the device. The 32−lead LQFP Package has a 7 x 7 mm2 body size
with conservative 0.8 mm pin spacing.
http://onsemi.com
MARKING
DIAGRAM
LQFP−32
CASE 873A
2I9940L
AWLYYWWG
2I9940L = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
Features
• LVPECL or LVCMOS Clock Input
• 2.5 V LVCMOS Outputs for Intel® Pentium® II
Microprocessor Support
• 150 pS Maximum Output−to−Output Skew
• Maximum Output Frequency of 250 MHz
• 32 Lead LQFP Package
• Dual or Single Supply Device:
♦ Dual VCC Supply Voltage, 3.3 V Core and 2.5 V
Output
♦ Single 3.3 V VCC Supply Voltage for 3.3 V Outputs
♦ Single 2.5 V VCC Supply Voltage for 2.5 V I/O
• Pin and Function compatible to MPC940L, MPC9109,
CY29940 and CY29940−1
• These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 0
1
Publication Order Number:
ASM2I9940L/D
1 page  
ASM2I9940L
Table 8. AC CHARACTERISTICS (TA = 0°C to 70°C, VCCI = 3.3 V $ 5%, VCCO = 2.5 V $ 5%)
Symbol
Characteristic
Condition
Min Typ Max Unit
Fmax
tPLH
Maximum Input Frequency
Propagation Delay
PECL_CLK v 150 MHz
CMOS_CLK v 150 MHz
(Note 4)
250 MHz
2.0 2.8 3.5 nS
1.7 2.5 3.0
tPLH Propagation Delay
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
2.0 2.9 3.8 nS
1.8 2.5 3.3
tsk(o)
Output−to−output Skew
PECL_CLK
CMOS_CLK
(Note 4)
150 pS
150
tsk(pp)
Part–to–Part Skew
PECL_CLK ≤ 150 MHz
CMOS_CLK ≤ 150 MHz
(Notes 4 and 5)
1.5 nS
1.3
tsk(pp)
Part–to–Part Skew
PECL_CLK > 150 MHz
CMOS_CLK > 150 MHz
(Notes 4 and 5)
1.8 nS
1.5
tsk(pp)
Part–to–Part Skew
PECL_CLK
CMOS_CLK
(Notes 4 and 6)
850 pS
750
DC Output Duty Cycle
fCLK < 134 MHz
fCLK v 250 MHz
tr, tf Output Rise/Fall Time
4. Tested using standard input levels, Production tested @ 150 MHz.
5. Across temperature and voltage ranges, includes output skew.
6. For a specific temperature and voltage, includes output skew.
Input DC = 50% 45 50 55
%
Input DC = 50% 40 50 60
0.5 – 1.8 V
0.3
1.2 nS
Table 9. DC CHARACTERISTICS (TA = 0°C to 70°C, VCCI = 2.5 V $ 5%, VCCO = 2.5 V $ 5%)
Symbol
Characteristic
Condition
Min
VIH
VIL
VPP
VCMR
VOH
VOL
IIN
CIN
Cpd
ZOUT
ICC
Input HIGH Voltage
CMOS_CLK
Input LOW Voltage
CMOS_CLK
Peak–to–Peak Input Voltage PECL_CLK
Common Mode Range
PECL_CLK
Output HIGH Voltage
Output LOW Voltage
Input Current
Input Capacitance
Power Dissipation Capacitance
Output Impedance
Maximum Quiescent Supply Current
IOH = –12 mA
IOL = 12 mA
per output
2.0
500
VCCI – 1.0
1.8
18
Typ
4.0
10
23
0.5
Max
VCCI
0.8
1000
VCCI – 0.6
0.5
$200
28
1.0
Unit
V
V
mV
V
V
V
mA
pF
pF
W
mA
http://onsemi.com
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