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PDF CM2009 Data sheet ( Hoja de datos )
| Número de pieza | CM2009 | |
| Descripción | VGA Port Companion Circuit | |
| Fabricantes | ON Semiconductor | |
| Logotipo |  |
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CM2009
VGA Port Companion
Circuit
Product Description
The CM2009 connects between a video graphics controller
embedded in a PC, graphics adapter card or set top box and the VGA
or DVI−I port connector. The CM2009 incorporates ESD protection
for all signals, level shifting for the DDC signals and buffering for the
SYNC signals. ESD protection for the video, DDC and SYNC lines is
implemented with low−capacitance current steering diodes.
All ESD diodes are designed to safely handle the high current spikes
specified by IEC−61000−4−2 Level 4 (±8 kV contact discharge if
CBYP is present, ±4 kV if not). The ESD protection for the DDC signal
pins are designed to prevent “back current” when the device is
powered down while connected to a monitor that is powered up.
Separate positive supply rails are provided for the VIDEO, DDC
and SYNC channels to facilitate interfacing with low voltage video
controller ICs to provide design flexibility in multi−supply−voltage
environments.
Two non−inverting drivers provide buffering for the HSYNC and
VSYNC signals from the video controller IC (SYNC1, SYNC2).
These buffers accept TTL input levels and convert them to CMOS
output levels that swing between Ground and VCC_SYNC, which is
typically 5 V. Additionally, each driver has a series termination resistor
(RT) connected to the SYNC_OUT pin, eliminating the external
termination resistors typically required for the HSYNC and VSYNC
lines of the video cable. There are three versions with different values
of RT to allow termination at typically 65 W (CM2009−00) or 15 W
(CM2009−02).
The 15 W (CM2009−02) version will typically require two external
resistors which can be chosen to exactly match the characteristic
impedance of the SYNC lines of the video cable.
Two N−channel MOSFETs provide the level shifting function
required when the DDC controller is operated at a lower supply
voltage than the monitor. The gate terminals for these MOSFETS
(VCC_DDC) should be connected to the supply rail (typically 3.3 V)
that supplies power to the transceivers of the DDC controller.
http://onsemi.com
QSOP16
QR SUFFIX
CASE 492
MARKING DIAGRAM
CMD YYWW
CM2009
0xQR
CM2009 0xQR = Specific Device Code
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
Shipping†
CM2009−00QR QSOP−16 2500/Tape & Reel
(Pb−Free)
CM2009−02QR QSOP−16 2500/Tape & Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Features
• Includes ESD Protection, Level−Shifting, Buffering and
Sync Impedance Matching
• 7 Channels of ESD Protection for all VGA Port
Connector Pins Meeting IEC−61000−4−2 Level 4 ESD
Requirements (±8 kV Contact Discharge)
• Very Low Loading Capacitance from ESD Protection
Diodes on VIDEO Lines (4 pF Maximum)
Applications
• VGA and DVI−I Ports in:
♦ Desktop and Notebook PCs
♦ Graphics Cards
♦ Set Top Boxes
• 5 V Drivers for HSYNC and VSYNC Lines
• Integrated Impedance Matching Resistors on Sync Lines
• Bi−directional Level Shifting N−Channel FETs
Provided for DDC_CLK & DDC_DATA Channels
• Backdrive Protection on DDC Lines
• Compact 16−Lead QSOP Package
• These Devices are Pb−Free and are RoHS Compliant
© Semiconductor Components Industries, LLC, 2012
May, 2012 − Rev. 5
1
Publication Order Number:
CM2009/D
1 page  
CM2009
APPLICATION INFORMATION
Figure 1. Typical Application Connection Diagram
NOTES:
1. The CM2009 should be placed as close to the VGA or DVI−I connector as possible.
2. The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B
signals.
3. If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with
external 37.5 W resistors.
4. “VF” are external video filters for the RGB signals.
5. Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins.
Connections to the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than
5 mm) for best ESD protection.
6. The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum
ESD withstand voltage at the DDC_OUT pins from ±8 kV to ±4 kV. If 8 kV ESD protection is required, a 0.2 mF
ceramic bypass capacitor should be connected between BYP and ground.
7. The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8. The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference
only. The component values and filter configuration may be changed to suit the application.
9. The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and
DDCA_DATA.
10. R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when
no monitor is connected to the VGA connector. If used, it should be noted that “back current” may flow between the
DDC pins and VCC_5V via these resistors when VCC_5V is powered down.
11. For optimal ESD performance with the CM2009−02, an additional clamp device (such as the CMD PACDN042)
should be placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector.
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5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CM2009.PDF ] | |
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