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PDF CM2009 Data sheet ( Hoja de datos )
| Número de pieza | CM2009 | |
| Descripción | VGA Port Companion Circuit | |
| Fabricantes | CMD | |
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CM2009
VGA Port Companion Circuit
Features
• Includes ESD protection, level-shifting, buffering
and sync impedance matching
• 7 channels of ESD protection for all VGA port con-
nector pins meeting IEC-61000-4-2 Level 4 ESD
requirements (±8kV contact discharge)
• Very low loading capacitance from ESD protection
diodes on VIDEO lines, 4pF maximum
• 5V drivers for HSYNC and VSYNC lines
• Integrated impedance matching resistors on sync
lines
• Bi-directional level shifting N-channel FETs pro-
vided for DDC_CLK & DDC_DATA channels
• Backdrive protection on DDC lines
• Compact 16-lead QSOP package
Applications
• VGA and DVI-I ports in:
- Desktop and Notebook PCs
- Graphics Cards
- Set Top Boxes
Product Description
The CM2009 connects between a video graphics con-
troller embedded in a PC, graphics adapter card or set
top box and the VGA or DVI-I port connector. The
CM2009 incorporates ESD protection for all signals,
level shifting for the DDC signals and buffering for the
SYNC signals. ESD protection for the video, DDC and
SYNC lines is implemented with low-capacitance cur-
rent steering diodes.
All ESD diodes are designed to safely handle the high
current spikes specified by IEC-61000-4-2 Level 4
(±8KV contact discharge if CBYP is present, ±4KV if
not). The ESD protection for the DDC signal pins are
designed to prevent "back current" when the device is
powered down while connected to a monitor that is
powered up.
Separate positive supply rails are provided for the
VIDEO, DDC and SYNC channels to facilitate interfac-
ing with low voltage video controller ICs to provide
design flexibility in multi-supply-voltage environments.
(cont’d next page)
Simplified Electrical Schematic
VIDEO_1
VIDEO_2
VIDEO_3
3
4
5
VCC_VIDEO
2
VCC_DDC
7
6
GND
DDC_IN1 10
DDC_IN2 11
SYNC_IN1 13
SYNC_IN2 15
GND
BYP
8
VCC_SYNC
1
9
DDC_OUT1
12 DDC_OUT2
RT RT
16 SYNC_OUT2
14 SYNC_OUT1
© 2004 California Micro Devices Corp. All rights reserved.
08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
1
1 page  
CM2009
Application Information
HSYNC
VSYNC
R1
100k
R2
100k
VCC_5V
VCCA_DAC
RED
GREEN
BLUE
C2
0.2uF
75 75 75
C1
0.2uF
VCC_SYNC
VCC_VIDEO
SYNC_OUT2
SYNC_IN2
SYNC_OUT1
SYNC_IN1
DDC_OUT2
DDC_IN2
DDC_IN1
DDC_OUT1
CM2009
VCCGPIO
** VIDEO Filters.
See Note 4
VIDEO_1
VIDEO_2
VIDEO_3
VCC_DDC
C11 FB4
C12
C9 FB3
C10
C7 FB2
C8
C5 FB1
C6
Optional EMI Filters
VSYNC_OUT
SYNC_GND
HSYNC_OUT
DDC_DATA
DIG_GND
DDC_CLK
RED_VIDEO
GREEN_VIDEO
BLUE_VIDEO
RED_GND
GREEN_GND
BLUE_GND
DDCA_CLK
DDCA_DATA
Video Port
Connector
Figure 1. Typical Application Connection Diagram
NOTES
1 The CM2009 should be placed as close to the VGA or DVI-I connector as possible.
2 The ESD protection channels VIDEO_1, VIDEO_2, VIDEO_3 may be used interchangeably between the R, G, B signals.
3 If differential video signal routing is used, the RED, BLUE, and GREEN signal lines should be terminated with external 37.5
resistors.
4 "VF" are external video filters for the RGB signals.
5 Supply bypass capacitors C1 and C2 must be placed immediately adjacent to the corresponding Vcc pins. Connections to
the Vcc pins and ground plane must be made with minimal length copper traces (preferably less than 5mm) for best ESD
protection.
6 The bypass capacitor for the BYP pin has been omitted in this diagram. This results in a reduction in the maximum ESD
withstand voltage at the DDC_OUT pins from ±8kV to ±4kV. If 8kV ESD protection is required, a 0.2µF ceramic bypass
capacitor should be connected between BYP and ground.
7 The SYNC buffers may be used interchangeably between HSYNC and VSYNC.
8 The EMI filters at the SYNC_OUT and DDC_OUT pins (C5 to C12, and Ferrite Beads FB1 to FB4) are for reference only.
The component values and filter configuration may be changed to suit the application.
9 The DDC level shifters DDC_IN, DDC_OUT, may be used interchangeably between DDCA_CLK and DDCA_DATA.
10 R1, R2 are optional. They may be used, if required, to pull the DDC_CLK and DDC_DATA lines to VCC_5V when no moni-
tor is connected to the VGA connector. If used, it should be noted that "back current" may flow between the DDC pins and
VCC_5V via these resistors when VCC_5V is powered down.
11 For optimal ESD performance with the CM2009-02, an additional clamp device (such as the CMD PACDN042) should be
placed on HSYNC/VSYNC lines between the external matching resistor and the VGA connector.
© 2004 California Micro Devices Corp. All rights reserved.
08/12/04 430 N. McCarthy Blvd., Milpitas, CA 95035-5112
▲ Tel: 408.263.3214 ▲ Fax: 408.263.7846 ▲ www.calmicro.com
5
5 Page | ||
| Páginas | Total 6 Páginas | |
| PDF Descargar | [ Datasheet CM2009.PDF ] | |
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