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PDF SH68F86 Data sheet ( Hoja de datos )
| Número de pieza | SH68F86 | |
| Descripción | Low Speed USB Micro-controller | |
| Fabricantes | Sino Wealth | |
| Logotipo |  |
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SH68F86
Low Speed USB Micro-controller
Features
8-bit CMOS Micro-Processor (uP) core
- Instruction set is compatible with standard 8051
- Build-in 12MHz RC for MCU clock
Memory
- 16K Bytes Flash
- Support USB Self-Sectors-Programming (SSP)
- 256 bytes internal data memory
Operation voltage 4.4V - 5.25V
3.3V regulator output
- Maximum driving current 35mA
Up to 13 general purpose I/O ports
Interrupt
- 10 vectors interrupt structure
- Timer0 & 1, USB, EX0
Two 8-Bit Base Timer
1 external Interrupt: EX0
Build-in 32KHz oscillator for programmable wake up timer
USB Specification Compliance
- Complies with USB specification 1.1
- Support one Low-Speed USB Device Address with 3
endpoints (endpoint 0, 1, and 2)
- Built-in 1.5Kohms USB pull-up resistor with DM
Built-in Watch Dog Timer (WDT)
Reset
- Hardware reset
- Power-on reset, Low-voltage reset
- USB reset
- Watch-Dog reset
- Resume reset
Two power-reducing modes:
- IDLE mode
- Power-Down mode
Package:
- 24 pad Chip Form
- 20 pin TSSOP
General Description
The SH68F86 is an enhanced 8051-compatiable micro-controller with integrated low-speed USB SIE, Transceiver and data
FIFO, build-in 1.8v for CPU core and 3.3v for USB transceiver, IO and others. With on-chip 16K bytes flash memory and internal
256 bytes data memory suit for variable applications. Two 8-bits timer, programmable Watch-dog timer and Wake-up timer
provide great F/W facility and power saving mode operation, 13 selectable GPIO in 20 pin TSSOP package, build-in 12MHz
oscillator to eliminate external crystal. Besides, build-in 32K oscillator, POR and LVR circuit will further saving your external
components cost. The SH68F86 is a highly integrated MCU designed for cost effective applications. Application can cover such
items as Dongle and others.
1 V2.0
1 page  
SH68F86
Functional Description
1. Memory
1.1. Memory Allocation
There are 16K bytes Program Memory and 256 bytes Data Memory. These features are described as followed.
1.2. Program Memory
The SH68F86 embeds 16K Bytes (0000H - 3FFFH) on-chip program memory for program code. The flash program memory
provides electrical erasure and programming.
1.3. Data Memory
The SH68F86 provides additional Bytes of RAM space for increased data parameter handling, high level language usage. The
SH68F86 has internal data memory that is mapped into three separate segments.
The Three segments are:
1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.
2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.
3. The Special Function Registers (SFR, addresses 80H to FFH) are directly addressable only.
The Upper 128 bytes of RAM occupy the same address space as SFR, but they are physically separate from SFR space. When
an instruction accesses an internal location above address 7Fh, the CPU can distinguish whether to access the upper 128 bytes
data RAM or to access SFR by different addressing mode of the instruction. Note the unused address is unavailable in SFR.
The Internal RAM configuration is shown as below:
0xFFFF
0x4000
Program Memory
(FLASH ROM)
RESERVED
0xFF
Data Memory
(Internal SRAM)
Upper 128 Bytes
(Indirect
Addressing Only)
Special Function
Register Area
(Direct Addressing
Only)
16K Bytes Flash ROM
For User's Code Segment
0x0000
0x80
0x7F
0x20
0x1F
0x00
Direct and Indirect
Addressing Area
General Purpose
Registers
Low 128 Bytes
Direct and Indirect
Addressing Ares
Figure 1-1. SH68F86 Program/Data Memory Map
5
5 Page 
3.3. Instruction Set List
ADD
ADDC
SUBB
INC
DEC
MUL
DIV
DA
Opcode
A, Rn
A, @Ri
A, direct
A, #data
A, Rn
A, @Ri
A, direct
A, #data
A, Rn
A, @Ri
A, direct
A, #data
A
Rn
@Ri
DPTR
direct
A
Rn
@Ri
direct
AB
AB
A
CLR
CPL
ANL
ORL
XRL
Opcode
A
A
A, Rn
A, @Ri
A, direct
A, #data
direct, A
direct, #data
A, Rn
A, @Ri
A, direct
A, #data
direct, A
direct, #data
A, Rn
A, @Ri
A, direct
A, #data
direct, A
direct, #data
SH68F86
Arithmetic Instructions
Bytes Cycles
Meaning
1 1 Add reg to acc
1 2 Add indir byte to acc
2 2 Add dir byte to acc
2 2 Add imm. Data to acc
1 1 Add reg to acc with carry flag
1 2 Add indir byte to acc with carry flag
2 2 Add dir byte to acc with carry flag
2 2 Add imm. Data to acc with carry flag
1 1 Subtract reg from acc with borrow
1 2 Subtract indir byte from acc with borrow
2 2 Subtract dir byte from acc with borrow
2 2 Subtract imm. Data from acc with borrow
1 1 Increment acc
1 2 Increment reg
1 3 Increment indir byte
1 4 Increment data pointer
2 3 Increment dir byte
1 1 Decrement acc
1 2 Decrement reg
1 3 Decrement indir byte
2 3 Decrement dir byte
1 11 Multiply A and B, 8-bit
1 20 Multiply (AUXC A) and B, 16-bit
1 11 Divide A by B, 8-bit
1 20 Divide (AUXC A) by B, 16-bit
1 1 Decimal adjust acc
Logical Instructions
Bytes Cycles
Meaning
11
Clear acc
1 1 Complement acc
1 1 AND register to acc
1 2 AND indir byte to acc
2 2 AND dir byte to acc
2 2 AND imm. Data to acc
2 3 AND acc to dir byte
3 3 AND imm. Data to dir byte
1 1 OR reg to acc
1 2 OR indir byte to acc
2 2 OR dir byte to acc
2 2 OR imm. Data to acc
2 3 OR acc to dir byte
3 3 OR imm. Data to dir byte
1 1 Exclusive-OR reg to acc
1 2 Exclusive-OR indir byte to acc
2 2 Exclusive-OR dir byte to acc
2 2 Exclusive-OR imm. Data to acc
2 3 Exclusive-OR acc to dir byte
3 3 Exclusive-OR imm. Data to dir byte
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet SH68F86.PDF ] | |
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