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PDF MCP3911 Data sheet ( Hoja de datos )
| Número de pieza | MCP3911 | |
| Descripción | 3.3V Two-Channel Analog Front End | |
| Fabricantes | Microchip | |
| Logotipo |  |
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MCP3911
3.3V Two-Channel Analog Front End
Features
• Two Synchronous Sampling 16/24-bit Resolution
Delta-Sigma A/D Converters
• 94.5 dB SINAD, -106.5 dBc Total Harmonic
Distortion (THD) (up to 35th harmonic), 111 dB
SFDR for Each Channel
• 2.7V – 3.6V AVDD, DVDD
• Programmable Data Rate up to 125 ksps
- 4 MHz Maximum Sampling Frequency
• Oversampling Ratio up to 4096
• Ultra Low Power Shutdown Mode with <2 µA
• -122 dB Crosstalk between the Two Channels
• LowDrift1.2VInternalVoltageReference:7 ppm/°C
• Differential Voltage Reference Input Pins
• High Gain Programmable Gain Amplifier (PGA)
on Each Channel (up to 32V/V)
• Phase Delay Compensation with 1 µs Time
Resolution
• Separate Modulator Output Pins for Each
Channel
• Separate Data Ready Pin for Easy
Synchronization
• Individual 24-bit Digital Offset and Gain Error
Correction for Each Channel
• High-Speed 20 MHz SPI Interface with Mode 0,0
and 1,1 Compatibility
• Continuous Read/Write Modes for Minimum
Communication
• Low Power Consumption (8.9 mW at 3.3V,
5.6 mW at 3.3V in low-power mode, typical)
• Available in Small 20-lead QFN and SSOP
Packages, Pin-to-pin Compatible with MCP3901
• Extended Temperature Range: -40°C to +125°C
Applications
• Energy Metering and Power Measurement
• Automotive
• Portable Instrumentation
• Medical and Power Monitoring
• Audio/Voice Recognition
Description
The MCP3911 is a 2.7V to 3.6V dual channel Analog
Front End (AFE) containing two synchronous sampling
Delta-Sigma Analog-to-Digital Converters (ADC), two
PGAs, phase delay compensation block, low-drift
internal voltage reference, modulator output block,
digital offset and gain errors calibration registers and
high-speed 20 MHz SPI compatible serial interface.
The MCP3911 ADCs are fully configurable with
features such as: 16/24-bit resolution, OSR from 32 to
4096, gain from 1x to 32x, independent shutdown and
reset, dithering and auto-zeroing. The communication
is largely simplified with the one-byte-long commands
including various continuous read/write modes that can
be accessed by the Direct Memory Access (DMA) of an
MCU with a separate data ready pin that can be directly
connected to an Interrupt Request (IRQ) input of an
MCU.
The MCP3911 is capable of interfacing a large variety
of voltage and current sensors including shunts,
current transformers, Rogowski coils and Hall effect
sensors.
Package Type
20-Lead
SSOP
RESET
DVDD
AVDD
CH0+
CH0-
CH1-
CH1+
AGND
REFIN+/OUT
REFIN-
1
2
3
4
5
6
7
8
9
10
20 SDI
19 SDO
18 SCK
17 CS
16 OSC2
15 OSC1/CLKI
14 DR
13 MDAT0
12 MDAT1
11 DGND
20-Lead
4x4 QFN*
20 19 18 17 16
CH0+ 1
15 SCK
CH0- 2
CH1- 3
EP 14 CS
21 13 OSC2
CH1+ 4
12 OSC1/CLKI
AGND 5
11 DR
6 7 8 9 10
2012-2013 Microchip Technology Inc.
* Includes Exposed Thermal Pad (EP); see Table 3-1.
DS20002286C-page 1
1 page  
MCP3911
TABLE 1-1: ANALOG SPECIFICATIONS TARGET TABLE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 2.7V to 3.6V, MCLK = 4 MHz;
PRE<1:0> = 00; OSR = 256; GAIN = 1; VREFEXT = 0, CLKEXT = 1, AZ_FREQ = 0, DITHER<1:0> = 11, BOOST<1:0> = 10;
VCM = 0V; TA = -40°C to +125°C; VIN = 1.2VPP = 424 mVRMS at 50/60 Hz on both channels.
Characteristic
Sym
Min Typ Max Units
Conditions
Internal Voltage Reference
Tolerance
Temperature Coefficient
VREF
TCVREF
1.176 1.2 1.224
V VREFEXT = 0,
TA = +25°C only
— 7 — ppm/°C TA = -40°C to +125°C,
VREFEXT = 0
Output Impedance
ZOUTVREF
—
2
—
kΩ VREFEXT = 0
Internal Voltage Refer-
AIDDVREF
—
25 —
µA VREFEXT = 0,
ence Operating Current
SHUTDOWN<1:0> = 11
Voltage Reference Input
Input Capacitance
— — 10 pF
Differential Input Voltage
Range (VREF+ – VREF-)
Absolute Voltage on
REFIN+ pin
VREF
VREF+
1.1 —
VREF- + 1.1 —
1.3
VREF-
+ 1.3
V VREFEXT = 1
V VREFEXT = 1
Absolute Voltage on
REFIN- pin
Master Clock Input
VREF-
-0.1 — +0.1
V REFIN- should be connected
to AGND when VREFEXT = 0
Master Clock Input
Frequency Range
fMCLK
— 20 MHz CLKEXT = 1, Note 6
Crystal Oscillator
Operating Frequency
Range
fXTAL
1 — 20 MHz CLKEXT = 0, Note 6
Analog Master Clock
AMCLK
— — 16 MHz Note 6
Power Supply
Operating Voltage, Ana-
log
AVDD
2.7 — 3.6
V
Operating Voltage, Digital
Operating Current,
Analog (Note 2)
DVDD
IDD,A
2.7 — 3.6
— 1.5 2.3
— 1.8 2.8
V
mA BOOST<1:0> = 00
mA BOOST<1:0> = 01
— 2.5 3.5 mA BOOST<1:0> = 10
—
4.4 6.25
mA BOOST<1:0> = 11
Note 1:
2:
3:
4:
5:
6:
This specification implies that the ADC output is valid over this entire differential range and that there is no distortion or
instability across this input range. Dynamic Performance specified at -0.5 dB below the maximum signal range,
VIN = 1.2VPP = 424 mVRMS, VREF = 1.2V at 50/60 Hz. See Section 4.0, Terminologies And Formulas for definition.
This parameter is established by characterization and not 100% tested. See performance graphs for other than default
settings provided here.
For these operating currents, the following configuration bit settings apply: SHUTDOWN<1:0> = 00,
RESET<1:0> = 00, VREFEXT = 0, CLKEXT = 0.
For these operating currents, the following configuration bit settings apply: SHUTDOWN<1:0> = 11, VREFEXT = 1,
CLKEXT = 1.
Applies to all gains. Offset and gain errors depend on PGA gain setting, see Section 2.0, Typical Performance
Curves for typical performance.
Outside of this range, the ADC accuracy is not specified. An extended input range of ±2 V can be applied continuously
to the part with no damage.
For proper operation and optimizing ADC accuracy, AMCLK should be limited to the maximum frequency defined in
Table 5-2 as a function of the BOOST and PGA settings chosen. MCLK can take larger values as long as the prescaler
settings (PRE<1:0>) limit AMCLK = MCLK/PRESCALE in the defined range in Table 5-2.
2012-2013 Microchip Technology Inc.
DS20002286C-page 5
5 Page 
MCP3911
2.0 TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
OSR = 256; GAIN = 1; Dithering = Maximum; VIN = -0.5 dBFS at 60 Hz, VREFEXT = 0; CLKEXT = 1, AZ_FREQ = 0;
BOOST = 1X.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0
fIN = -0.5 dBFS @ 60 Hz
fD = 3.9 ksps
16384 pt FFT
OSR = 256
Dithering = None
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
FIGURE 2-1:
Spectral Response.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0
fIN = -0.5 dBFS @ 60 Hz
fD = 3.9 ksps
16384 pt FFT
OSR = 256
Dithering = Maximum
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
FIGURE 2-4:
Spectral Response.
0
-20
-40
-60
-80
-100
fIN = -60 dBFS@ 60 Hz
fD = 3.9 ksps
16384 pt FFT
OSR = 256
Dithering = None
-120
-140
-160
-180
-200
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
FIGURE 2-2:
Spectral Response.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0
fIN = -60 dBFS @ 60 Hz
fD = 3.9 ksps
16384 pt FFT
OSR = 256
Dithering = Maximum
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
FIGURE 2-5:
Spectral Response.
-107.3 -107.1 -107.0 -106.8 -106.7 -106.5 -106.4 -106.2 -106.1 -105.9 -105.8
Total Harmonic Distortion (-dBc)
FIGURE 2-3:
THD Histogram.
94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5
Signal-to-Noise and Distortion Ratio (dB)
FIGURE 2-6:
SINAD Histogram.
2012-2013 Microchip Technology Inc.
DS20002286C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MCP3911.PDF ] | |
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