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PDF MPC8275 Data sheet ( Hoja de datos )
| Número de pieza | MPC8275 | |
| Descripción | PowerQUICC II Family Hardware Specifications | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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Freescale Semiconductor
Technical Data
Document Number: MPC8280EC
Rev. 2, 09/2011
MPC8280
PowerQUICC II Family
Hardware Specifications
This document contains detailed information about power
considerations, DC/AC electrical characteristics, and AC
timing specifications for .13µm (HiP7) members of the
PowerQUICC II family of integrated communications
processors—the MPC8280, the MPC8275, and the
MPC8270 (collectively called the MPC8280 throughout this
document).
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 12
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 16
7. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 26
8. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
9. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 75
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 79
11. Document Revision History . . . . . . . . . . . . . . . . . . . 79
© 2011 Freescale Semiconductor, Inc. All rights reserved.
1 page  
Overview
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8280) required by the PCI standard as well as message and
doorbell registers
— Supports the I2O standard
— Hot-swap friendly (supports the hot swap specification as defined by PICMG 2.1 R1.0 August
3, 1998)
— Support for 66.67/83.33/100 MHz, 3.3 V specification
— 60x-PCI bus core logic that uses a buffer pool to allocate buffers for each port
— Uses the local bus signals, removing need for additional pins
• System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1 JTAG test access port
• 12-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other
user-definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user-programmable machines, general-purpose chip-select machine, and page mode
pipeline SDRAM machine
— Byte selects for 64-bit bus width (60x) and byte selects for 32-bus width (local)
— Dedicated interface logic for SDRAM
• CPU core can be disabled and the device can be used in slave mode to an external core
• Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications protocols
— Interfaces to G2_LE core through an on-chip 32 KB dual-port data RAM, an on-chip 32 KB
dual-port instruction RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII) or reduced media independent interface (RMII)
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
Freescale Semiconductor
5
5 Page 
DC Electrical Characteristics
Table 5. DC Electrical Characteristics1 (continued)
Characteristic
Symbol
Min
Max Unit
IOL = 5.3mA
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
LWR
MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0–2]
IOL = 3.2mA
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTAL_A30/REQ2
L_A31
LCL_D[0-31)]/AD[0-31]
LCL_DP[03]/C/BE[0-3]
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
QREQ
VOL — 0.4 V
1 The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive DC
current, either pull unused pins to GND or VDDH or configure them as outputs.
2 TCK, TRST and PORESET have min VIH = 2.5V.
3 The leakage current is measured for nominal VDDH,VCCSYN, and VDD.
MPC8280 PowerQUICC II Family Hardware Specifications, Rev. 2
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MPC8275.PDF ] | |
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