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PDF MPC8272 Data sheet ( Hoja de datos )
| Número de pieza | MPC8272 | |
| Descripción | PowerQUICC II Family Hardware Specifications | |
| Fabricantes | Motorola Semiconductors | |
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Freescale Semiconductor
Technical Data
Document Number: MPC8272EC
Rev. 3, 09/2011
MPC8272
PowerQUICC II Family
Hardware Specifications
This document contains detailed information about power
considerations, DC/AC electrical characteristics, and AC
timing specifications for .13µm (HiP7) members of the
PowerQUICC II family of integrated communications
processors—the MPC8272, the MPC8248, the MPC8271,
and the MPC8247. They include on a single chip a 32-bit
Power Architecture® core that incorporates memory
management units (MMUs) and instruction and data caches
and that implements the Power Architecture instruction set;
a modified communications processor module (CPM); and
an integrated security engine (SEC) for encryption (the
MPC8272 and the MPC8248 only).
All four devices are collectively referred to throughout this
hardware specification as “the MPC8272” unless otherwise
noted.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7
3. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9
4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 14
5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 18
7. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 27
8. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 56
10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 58
11. Document Revision History . . . . . . . . . . . . . . . . . . . 58
© 2011 Freescale Semiconductor, Inc. All rights reserved.
1 page  
Overview
• Integrated security engine (SEC) (MPC8272 and MPC8248 only)
— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms
in hardware
• Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications peripherals
— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port
RAM size is 16 KB plus 4 KB dedicated instruction RAM.)
— Microcode tracing capabilities
— Eight CPM trap registers
• Universal serial bus (USB) controller
— Supports USB 2.0 full/low rate compatible
— USB host mode
– Supports control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– NRZI encoding/decoding with bit stuffing
– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and
data rate configuration). Note that low-speed operation requires an external hub.
– Flexible data buffers with multiple buffers per frame
– Supports local loopback mode for diagnostics (12 Mbps only)
— Supports USB slave mode
– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers
– CRC16 generation and checking
– CRC5 checking
– NRZI encoding/decoding with bit stuffing
– 12- or 1.5-Mbps data rate
– Flexible data buffers with multiple buffers per frame
– Automatic retransmission upon transmit error
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Two fast communication controllers (FCCs) supporting the following protocols:
– 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—up to T3 rates (clear channel)
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
5
5 Page 
DC Electrical Characteristics
Table 5. DC Electrical Characteristics1 (continued)
Characteristic
Symbol
Min
Max Unit
IOL = 5.3mA
CS[0–5]
CS6/BCTL1/SMI
CS7/TLBSYNC
BADDR27/ IRQ1
BADDR28/ IRQ2
ALE/ IRQ4
BCTL0
PWE[0–7]/PSDDQM[0–7]/PBS[0–7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4
PSDAMUX/PGPL5
PCI_CFG0 (PCI_HOST_EN)
PCI_CFG1 (PCI_ARB_EN)
PCI_CFG2 (DLL_ENABLE)
MODCK1/RSRV/TC(0)/BNKSEL(0)
MODCK2/CSE0/TC(1)/BNKSEL(1)
MODCK3CSE1/TC(2)/BNKSEL(2)
IOL = 3.2mA
PCI_PAR
PCI_FRAME
PCI_TRDY
PCI_IRDY
PCI_STOP
PCI_DEVSEL
PCI_IDSEL
PCI_PERR
PCI_SERR
PCI_REQ0
PCI_REQ1/ CPI_HS_ES
PCI_GNT0
PCI_GNT1/ CPI_HS_LES
PCI_GNT2/ CPI_HS_ENUM
PCI_RST
PCI_INTA
PCI_REQ2
DLLOUT
PCI_AD(0-31)
PCI_C(0–3)/BE(0-3)
PA[8–31]
PB[18–31]
PC[0–1,4–29]
PD[7–25, 29–31]
TDO
VOL — 0.4 V
1 The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent
excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs.
2 TCK, TRST and PORESET have min VIH = 2.5V.
3 VIL for IIC interface does not match IIC standard, but does meet IIC standard for VOL and should not cause any compatibility
issue.
4 The leakage current is measured for nominal VDDH,VCCSYN, and VDD.
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
Freescale Semiconductor
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet MPC8272.PDF ] | |
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