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PDF DS90C365 Data sheet ( Hoja de datos )
| Número de pieza | DS90C365 | |
| Descripción | (DS90C365 / DS90C385) +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display (FPD) Link-85 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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January 1999
DS90C385/DS90C365
+3.3V Programmable LVDS Transmitter 24-Bit Flat Panel
Display (FPD) Link-85 MHz, +3.3V Programmable LVDS
Transmitter 18-Bit Flat Panel Display (FPD) Link-85 MHz
General Description
The DS90C385 transmitter converts 28 bits of CMOS/TTL
data into four LVDS (Low Voltage Differential Signaling) data
streams. A phase-locked transmit clock is transmitted in par-
allel with the data streams over a fifth LVDS link. Every cycle
of the transmit clock 28 bits of input data are sampled and
transmitted. At a transmit clock frequency of 85 MHz, 24 bits
of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 595
Mbps per LVDS data channel. Using a 85 MHz clock, the
data throughput is 297.5 Mbytes/sec. Also available is the
DS90C365 that converts 21 bits of CMOS/TTL data into
three LVDS (Low Voltage Differential Signaling) data
streams. Both transmitters can be programmed for Rising
edge strobe or Falling edge strobe through a dedicated pin.
A Rising edge or Falling edge strobe transmitter will interop-
erate with a Falling edge strobe Receiver (DS90CF386/
DS90CF366) without any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 85 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption <130 mW (typ) @85MHz
Grayscale
n Tx Power-down mode <200µW (max)
n Supports VGA, SVGA, XGA and Single/Dual Pixel
SXGA.
n Narrow bus reduces cable size and cost
n Up to 2.38 Gbps throughput
n Up to 297.5 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 56-lead or 48-lead TSSOP package
Block Diagrams
DS90C385
DS90C365
DS100868-1
Order Number DS90C385MTD
See NS Package Number MTD56
DS100868-29
Order Number DS90C365MTD
See NS Package Number MTD48
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS100868
www.national.com
1 page  
AC Timing Diagrams (Continued)
FIGURE 2. “16 Grayscale” Test Pattern - DS90C385 (Notes 8, 9, 10)
DS100868-5
5 www.national.com
5 Page 
AC Timing Diagrams (Continued)
FIGURE 16. Timing Diagram of the Input cycle-to-cycle clock jitter
DS90C385 Pin Description — FPD Link Transmitter
DS100868-28
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
R_FB
TxCLK OUT+
TxCLK OUT−
PWR DOWN
VCC
GND
PLL VCC
PLL GND
LVDS VCC
LVDS GND
I/O No.
I 28
O4
O4
I1
I1
O1
O1
I1
I3
I4
I1
I2
I1
I3
Description
TTL level input. This includes: 8 Red, 8 Green, 8 Blue, and 4 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differentiaI data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
Negative LVDS differential clock output.
TTL level input. When asserted (low input) TRI-STATES the outputs, ensuring low current at
power down.
Power supply pins for TTL inputs.
Ground pins for TTL inputs.
Power supply pin for PLL.
Ground pins for PLL.
Power supply pin for LVDS outputs.
Ground pins for LVDS outputs.
DS90C365 Pin Description — FPD Link Transmitter
Pin Name
TxIN
TxOUT+
TxOUT−
FPSHIFT IN
R_FB
TxCLK OUT+
TxCLK OUT−
I/O No.
I 21
O3
O3
I1
I1
O1
O1
Description
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
Positive LVDS differential data output.
Negative LVDS differential data output.
TTL Ievel clock input. Pin name TxCLK IN.
Programmable strobe select (See Table 1).
Positive LVDS differential clock output.
Negative LVDS differential clock output.
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS90C365.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90C363 | +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link65 MHz/ +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link65 MHz | National Semiconductor |
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| DS90C363A | DS90C363A/CF363 3.3V Prog LVDS Trans 18Bit FPD Link - 65MHz (Rev. E) | Texas Instruments |
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