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PDF DS90C363A Data sheet ( Hoja de datos )
| Número de pieza | DS90C363A | |
| Descripción | +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz | |
| Fabricantes | National Semiconductor | |
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June 1998
DS90C363A/DS90CF363A
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link-65 MHz
+3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD)
Link-65 MHz
General Description
The DS90C363A/DS90CF363A transmitter converts 21 bits
of CMOS/TTL data into three LVDS (Low Voltage Differential
Signaling) data streams. A phase-locked transmit clock is
transmitted in parallel with the data streams over a fourth
LVDS link. Every cycle of the transmit clock 21 bits of input
data are sampled and transmitted. At a transmit clock fre-
quency of 65 MHz, 18 bits of RGB data and 3 bits of LCD
timing and control data (FPLINE, FPFRAME, DRDY) are
transmitted at a rate of 455 Mbps per LVDS data channel.
Using a 65 MHz clock, the data throughput is 170 Mbytes/
sec. The DS90C363A transmitter can be programmed for
Rising edge strobe or Falling edge strobe through a dedi-
cated pin. The DS90CF363A is fixed as a Falling edge
strobe transmitter. A Rising edge or Falling edge strobe
transmitter will interoperate with a Falling edge strobe Re-
ceiver (DS90CF364) without any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clock support
n Rejects > ± 3ns Jitter from VGA chip with less than
225ps output Jitter @65MHz (TJCC)
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption <130 mW (typ) @65MHz
Grayscale
n >50% Less Power Dissipation than BiCMOS
Alternatives
n Tx Power-down mode <200µW (max)
n ESD rating >7 kV (HBM), >500V (EIAJ)
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.3 Gbps throughput
n Up to 170 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
n Improved replacement for:
SN75LVDS85 — DS90C363A
SN75LVDS84 — DS90CF363A
Block Diagrams
DS90C363A/DS90CF363A
DS100138-1
Order Number DS90C363AMTD or DS90CF363AMTD
See NS Package Number MTD48
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100138
www.national.com
1 page  
AC Timing Diagrams (Continued)
DS100138-6
FIGURE 4. DS90C363A/DS90CF363A (Transmitter) LVDS Transition Times
DS100138-8
FIGURE 5. DS90C363A/DS90CF363A (Transmitter) Input Clock Transition Time
DS100138-10
FIGURE 6. DS90C363A/DS90CF363A (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
DS100138-12
FIGURE 7. DS90C363A/DS90CF363A (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
DS100138-14
FIGURE 8. DS90C363A/DS90CF363A (Transmitter) Phase Lock Loop Set Time
5
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Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90C363 | +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link65 MHz/ +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link65 MHz | National Semiconductor |
| DS90C363 | DS90C363/F364 3.3V Prog LVDS Trnsmit 18Bit FPD 65MHz/LVDS Rcvr 18Bit FPD 85MHz (Rev. C) |  Texas Instruments |
| DS90C363A | +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz | National Semiconductor |
| DS90C363A | DS90C363A/CF363 3.3V Prog LVDS Trans 18Bit FPD Link - 65MHz (Rev. E) | Texas Instruments |
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