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PDF DS90C363 Data sheet ( Hoja de datos )
| Número de pieza | DS90C363 | |
| Descripción | +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link65 MHz/ +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link65 MHz | |
| Fabricantes | National Semiconductor | |
| Logotipo |  |
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September 1999
DS90C363/DS90CF364
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link— 65 MHz, +3.3V LVDS Receiver
18-Bit Flat Panel Display (FPD) Link— 65 MHz
General Description
The DS90C363 transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. The DS90CF364 receiver converts the
LVDS data streams back into 21 bits of CMOS/TTL data. At
a transmit clock frequency of 65 MHz, 18 bits of RGB data
and 3 bits of LCD timing and control data (FPLINE,
FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per
LVDS data channel. Using a 65 MHz clock, the data through-
puts is 170 Mbytes/sec. The Transmitter is offered with pro-
grammable edge data strobes for convenient interface with a
variety of graphics controllers. The Transmitter can be pro-
grammed for Rising edge strobe or Falling edge strobe
through a dedicated pin. A Rising edge Transmitter will inter-
operate with a Falling edge Receiver (DS90CF364) without
any translation logic.
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Features
n 20 to 65 MHz shift clock support
n Programmable Transmitter (DS90C363) strobe select
(Rising or Falling edge strobe)
n Single 3.3V supply
n Chipset (Tx + Rx) power consumption < 250 mW (typ)
n Power-down mode (< 0.5 mW total)
n Single pixel per clock XGA (1024x768) ready
n Supports VGA, SVGA, XGA and higher addressability.
n Up to 170 Megabyte/sec bandwidth
n Up to 1.3 Gbps throughput
n Narrow bus reduces cable size and cost
n 290 mV swing LVDS devices for low EMI
n PLL requires no external components
n Low profile 48-lead TSSOP package
n Falling edge data strobe Receiver
n Compatible with TIA/EIA-644 LVDS standard
n ESD rating > 7 kV
n Operating Temperature: −40˚C to +85˚C
Block Diagrams
Application
DS012886-14
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1999 National Semiconductor Corporation DS012886
www.national.com
1 page  
Transmitter Switching Characteristics
Over recommended operating supply and −40˚C to +85˚C ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
Units
LLHT
LVDS Low-to-High Transition Time (Figure 3 )
0.75
1.5 ns
LHLT
LVDS High-to-Low Transition Time (Figure 3 )
0.75
1.5 ns
TCIT
TxCLK IN Transition Time (Figure 5 )
5 ns
TCCS
TxOUT Channel-to-Channel Skew (Figure 6 )
250 ps
TPPos0
Transmitter Output Pulse Position for Bit 0
(Figure 17 )
f = 65 MHz
−0.4
0
0.3 ns
TPPos1 Transmitter Output Pulse Position for Bit 1
1.8 2.2 2.5 ns
TPPos2 Transmitter Output Pulse Position for Bit 2
4.0 4.4 4.7 ns
TPPos3 Transmitter Output Pulse Position for Bit 3
6.2 6.6 6.9 ns
TPPos4 Transmitter Output Pulse Position for Bit 4
8.4 8.8 9.1 ns
TPPos5 Transmitter Output Pulse Position for Bit 5
10.6
11.0
11.3
ns
TPPos6 Transmitter Output Pulse Position for Bit 6
12.8
13.2
13.5
ns
TCIP
TxCLK IN Period (Figure 7)
15 T 50 ns
TCIH
TxCLK IN High Time (Figure 7)
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (Figure 7)
0.35T
0.5T
0.65T
ns
TSTC
TxIN Setup to TxCLK IN (Figure 7 )
f = 65 MHz
2.5
ns
THTC
TxIN Hold to TxCLK IN (Figure 7 )
0 ns
TCCD
TPLLS
TxCLK IN to TxCLK OUT Delay 25˚C, VCC = 3.3V (Figure 9 )
Transmitter Phase Lock Loop Set (Figure 11 )
3.0 3.7 5.5 ns
10 ms
TPDD
Transmitter Power Down Delay (Figure 15 )
100 ns
5 www.national.com
5 Page 
AC Timing Diagrams (Continued)
FIGURE 17. Transmitter LVDS Output Pulse Position Measurement
DS012886-22
11 www.national.com
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet DS90C363.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| DS90C363 | +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link65 MHz/ +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link65 MHz | National Semiconductor |
| DS90C363 | DS90C363/F364 3.3V Prog LVDS Trnsmit 18Bit FPD 65MHz/LVDS Rcvr 18Bit FPD 85MHz (Rev. C) |  Texas Instruments |
| DS90C363A | +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz/ +3.3V LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link-65 MHz | National Semiconductor |
| DS90C363A | DS90C363A/CF363 3.3V Prog LVDS Trans 18Bit FPD Link - 65MHz (Rev. E) | Texas Instruments |
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