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PDF AD9609 Data sheet ( Hoja de datos )
| Número de pieza | AD9609 | |
| Descripción | 1.8V Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9609
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
61.5 dBFS at 9.7 MHz input
61.0 dBFS at 200 MHz input
SFDR
75 dBc at 9.7 MHz input
73 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
76 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.10 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
FUNCTIONAL BLOCK DIAGRAM
AVDD
GND SDIO SCLK CSB
DRVDD
RBIAS
VCM
VIN+
VIN–
VREF
SENSE
SPI
PROGRAMMING DATA
ADC
CORE
REF
SELECT
DIVIDE
BY
1 TO 8
DCS
AD9609
MODE
CONTROLS
OR
D9 (MSB)
D0 (LSB)
DCO
CLK+ CLK–
PDWN DFS MODE
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD9609 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2. The sample-and-hold circuit maintains excellent performance
for input frequencies up to 200 MHz and is designed for low
cost, low power, and ease of use.
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D9 to D0) timing and offset adjustments, and voltage
reference modes.
4. The AD9609 is packaged in a 32-lead RoHS compliant
LFCSP that is pin compatible with the AD9629 12-bit ADC
and the AD9649 14-bit ADC, enabling a simple migration
path between 10-bit and 14-bit converters sampling from
20 MSPS to 80 MSPS.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
AD9609
Data Sheet
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 1.8 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, 50% duty
cycle clock, DCS disabled, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error1
Differential Nonlinearity (DNL)2
Integral Nonlinearity (INL)2
TEMPERATURE DRIFT
Offset Error
INTERNAL VOLTAGE REFERENCE
Output Voltage (1 V Mode)
Load Regulation Error at 1.0 mA
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance3
Input Common-Mode Voltage
Input Common-Mode Range
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD2
IDRVDD2 (1.8 V)
IDRVDD2 (3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input2 (DRVDD = 1.8 V)
Sine Wave Input2 (DRVDD = 3.3 V)
Standby Power4
Power-Down Power
Temp
Full
Full
Full
Full
Full
25°C
Full
25°C
Full
Full
Full
25°C
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
AD9609-20/AD9609-40
Min Typ
Max
10
−0.45
Guaranteed
+0.05
+0.55
−1.5
±0.15/±0.25
±0.05/±0.08
±0.35
±0.15
±2
0.984 0.996
2
1.008
0.06
2
6
0.9
0.5
7.5
1.3
1.7 1.8
1.7
1.9
3.6
24.9/29.7
1.4/2.2
2.5/4.1
27.0/32.0
45.2/54.7
46.3/57.4
53.1/67.0
34
0.5
52.0/61.0
AD9609-65
Min Typ Max
10
Guaranteed
−0.45 +0.05 +0.55
−1.5
±0.25
±0.15
±0.45
±0.15
±2
0.984 0.996 1.008
2
0.08
2
6
0.9
0.5 1.3
7.5
1.7 1.8 1.9
1.7 3.6
37.1 39.5
3.6
6.6
67.7
73.3 78.0
88.6
34
0.5
AD9609-80
Min Typ Max
10
Guaranteed
−0.45 +0.05 +0.55
−1.5
±0.25
±0.07
±0.45
±0.15
±2
0.984 0.996 1.008
2
0.08
2
6
0.9
0.5 1.3
7.5
1.7 1.8 1.9
1.7 3.6
41.8 45
4.3
7.9
76.3
83.0 92
89.5
34
0.5
Unit
Bits
% FSR
% FSR
LSB
LSB
LSB
LSB
ppm/°C
V
mV
LSB rms
V p-p
pF
V
V
kΩ
V
V
mA
mA
mA
mW
mW
mW
mW
mW
1 Measured with 1.0 V external reference.
2 Measured with a 10 MHz input frequency at rated sample rate, full-scale sine wave, with approximately 5 pF loading on each output bit.
3 Input capacitance refers to the effective capacitance between one differential input pin and AGND.
4 Standby power is measured with a dc input and the CLK active.
Rev. A | Page 4 of 32
5 Page 
AD9609
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
CLK+ 1
CLK– 2
AVDD 3
CSB 4
SCLK/DFS 5
SDIO/PDWN 6
NIC 7
NIC 8
AD9609
TOP VIEW
(Not to Scale)
24 AVDD
23 MODE/OR
22 DCO
21 D9 (MSB)
20 D8
19 D7
18 D6
17 D5
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PADDLE. THE EXPOSED PADDLE IS THE ONLY GROUND CONNECTION.
IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB
TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION,
NOISE, AND MECHANICAL STRENGTH BENEFITS.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic Description
0
EPAD
Exposed Paddle. The exposed paddle is the only ground connection. It must be soldered to the analog
ground of the PCB to ensure proper functionality and heat dissipation, noise, and mechanical strength
benefits.
1, 2 CLK+, CLK− Differential Encode Clock for PECL, LVDS, or 1.8 V CMOS Inputs.
3, 24, 29, 32
AVDD
1.8 V Supply Pin for ADC Core Domain.
4 CSB SPI Chip Select. Active low enable, 30 kΩ internal pull-up.
5
SCLK/DFS
SPI Clock Input in SPI Mode (SCLK). 30 kΩ internal pull-down.
Data Format Select in Non-SPI Mode (DFS). Static control of data output format. 30 kΩ internal pull-down.
DFS high = twos complement output; DFS low = offset binary output.
6 SDIO/PDWN SPI Data Input/Output (SDIO). Bidirectional SPI data I/O with 30 kΩ internal pull-down.
Non-SPI Mode Power-Down (PDWN). Static control of chip power-down with 30 kΩ internal pull-
down. See Table 15 for details.
7 to 10
NIC No Internal Connection.
11 to 12, 14 to 21 D0 (LSB) to
D9 (MSB)
ADC Digital Outputs.
13
DRVDD
1.8 V to 3.3 V Supply Pin for Output Driver Domain.
22 DCO Data Clock Digital Output.
23
MODE/OR
Chip Mode Select Input (MODE)/Out-of-Range Digital Output in SPI Mode (OR).
Default = out-of-range (OR) digital output (SPI Register 0x2A, Bit 0 = 1).
Option = chip mode select input (SPI Register 0x2A, Bit 0 = 0).
Chip power-down (SPI Register 0x08, Bits[7:5] = 100b).
Chip stand-by (SPI Register 0x08, Bits[7:5] = 101b).
Normal operation, output disabled (SPI Register 0x08, Bits[7:5] = 110b).
Normal operation, output enabled (SPI Register 0x08, Bits[7:5] = 111b).
Out-of-range (OR) digital output only in non-SPI mode.
25
VREF
1.0 V Voltage Reference Input/Output. See Table 10.
26
SENSE
Reference Mode Selection. See Table 10.
27 VCM Analog Output Voltage at Mid AVDD Supply. Sets common mode of the analog inputs.
28
RBIAS
Set Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground.
30, 31
VIN−, VIN+ ADC Analog Inputs.
Rev. A | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9609.PDF ] | |
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