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PDF AD9608 Data sheet ( Hoja de datos )
| Número de pieza | AD9608 | |
| Descripción | 1.8V Dual Analog-to-Digital Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
1.8 V analog supply operation
1.8 V CMOS or 1.8 V LVDS output
SNR = 61.7 dBFS at 70 MHz
SFDR = 85 dBc at 70 MHz
Low power: 71 mW/channel ADC core at 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.13 LSB
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
I/Q demodulation systems
Broadband data applications
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
10-Bit, 125/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter (ADC)
AD9608
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
SDIO SCLK CSB
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
REF
SELECT
SPI
ADC
PROGRAMMING DATA
AD9608
ADC
DIVIDE DUTY CYCLE
1 TO 8 STABILIZER
MODE
CONTROLS
ORA
D9A
D0A
DCOA
DRVDD
ORB
D9B
D0B
DCOB
CLK+ CLK–
SYNC
DCS
PDWN DFS OEB
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
Figure 1.
PRODUCT HIGHLIGHTS
1. Operates from a single 1.8 V analog power supply and
features a separate digital output driver supply to accom-
modate 1.8 V CMOS or 1.8 V LVDS logic families.
2. Provides a patented sample-and-hold circuit that maintains
excellent performance for input frequencies up to 200 MHz
and is designed for low cost, low power, and ease of use.1
3. Includes a standard serial port interface that supports various
product features and functions, such as data output format-
ting, internal clock divider, power-down, DCO/data timing,
and offset adjustments.
4. Packaged in a 64-lead, RoHS-compliant LFCSP that is pin
compatible with the AD9650, AD9269, and AD9268 16-bit
ADCs, the AD9258 and AD9648 14-bit ADCs, the AD9628
and AD9231 12-bit ADCs, and the AD9204 10-bit ADC,
enabling a simple migration path between 10-bit and 16-bit
converters sampling from 20 MSPS to 125 MSPS.
1 This product is protected by a U.S. patent.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
Free Datasheet http://www.datasheet4u.com/
1 page  
AD9608
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.0 V internal reference, DCS enabled, unless
otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 9.7 MHz
fIN = 30.5 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 200 MHz
TWO-TONE SFDR
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
CROSSTALK2
ANALOG INPUT BANDWIDTH
Temp
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
Full
25°C
Min
61.3
61.1
75
AD9608-105
Typ Max
61.7
61.7
61.7
61.6
61.4
61.6
61.6
61.6
61.5
61.3
9.9
9.9
9.9
9.9
9.9
−90
−89
−89
−75
−89
−84
85
85
85
85
84
−85
−85
−85
−75
−85
−85
82
−95
650
AD9608-125
Min Typ Max
61.7
61.7
61.7
61.3
61.6
61.4
61.6
61.6
61.6
61.1
61.5
61.3
9.9
9.9
9.9
9.9
9.9
−90
−89
−89
−75
−89
−84
85
85
85
75
85
84
−85
−85
−85
−75
−85
−85
82
−95
650
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dB
MHz
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
2 Crosstalk is measured at 100 MHz with −1.0 dBFS on one channel and no input on the alternate channel.
Rev. 0 | Page 5 of 40
Free Datasheet http://www.datasheet4u.com/
5 Page 
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
CLK+ 1
CLK– 2
SYNC 3
NC 4
NC 5
NC 6
NC 7
NC 8
NC 9
DRVDD 10
D0B (LSB) 11
D1B 12
D2B 13
D3B 14
D4B 15
D5B 16
PIN 1
INDICATOR
AD9608
PARALLEL CMOS
TOP VIEW
(Not to Scale)
48 PDWN
47 OEB
46 CSB
45 SCLK/DFS
44 SDIO/DCS
43 ORA
42 D9A (MSB)
41 D8A
40 D7A
39 D6A
38 D5A
37 DRVDD
36 D4A
35 D3A
34 D2A
33 D1A
AD9608
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES
THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE
CONNECTED TO GROUND FOR PROPER OPERATION.
Figure 6. Parallel CMOS Pin Configuration (Top View)
Table 8. Pin Function Descriptions (Parallel CMOS Mode)
Pin No.
Mnemonic
Type
Description
ADC Power Supplies
10, 19, 28, 37
DRVDD
Supply
Digital Output Driver Supply (1.8 V Nominal).
49, 50, 53, 54,
59, 60, 63, 64
AVDD
Supply
Analog Power Supply (1.8 V Nominal).
4, 5, 6, 7, 8, 9,
25, 26, 27, 29,
30, 31
NC
No Connect. Do not connect to this pin.
0
AGND,
Ground
The exposed thermal pad on the bottom of the package provides the analog ground
Exposed Pad
for the part. This exposed pad must be connected to ground for proper operation.
ADC Analog
51
VIN+A
Input
Differential Analog Input Pin (+) for Channel A.
52
VIN−A
Input
Differential Analog Input Pin (−) for Channel A.
62
VIN+B
Input
Differential Analog Input Pin (+) for Channel B.
61
VIN−B
Input
Differential Analog Input Pin (−) for Channel B.
55
VREF
Input/Output Voltage Reference Input/Output.
56
SENSE
Input
Reference Mode Selection.
58
RBIAS
Input/Output External Reference Bias Resistor.
57
VCM
Output
Common-Mode Level Bias Output for Analog Inputs.
1
CLK+
Input
ADC Clock Input—True.
2
CLK−
Input
ADC Clock Input—Complement.
Rev. 0 | Page 11 of 40
Free Datasheet http://www.datasheet4u.com
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9608.PDF ] | |
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