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PDF AS6C2008 Data sheet ( Hoja de datos )
| Número de pieza | AS6C2008 | |
| Descripción | 256K X 8 BIT LOW POWER CMOS SRAM | |
| Fabricantes | Alliance Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AS6C2008 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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February 2007
Rev. 1.1
AS6C2008
®
256K X 8 BIT LOW POWER CMOS SRAM
FEATURES
Access time : 55ns
Low power consumption:
Operating current :20mA (TYP.)
Standby current :
1µ A (TYP.) LL-version
Single 2.7V ~ 3.6V power supply
Fully static operation
Tri-state output
Data retention voltage : 1.5V (MIN.)
All Products ROHS Compliant
Package : 32-pin 450 mil SOP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm sTSOP
36-ball 6mm x 8mm TFBGA
PRODUCT FAMILY
Product
Family
Operating
Temperature
Vcc Range
GENERAL DESCRIPTION
The AS6C2008 is a 2,097,152-bit low power CMOS
static random access memory organized as 262,144
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The AS6C2008 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The AS6C2008 operates from a single power
supply of 2.7V ~ 3.6V
.
Speed
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
AS6C2008 (I)
-40 ~ 85ºC
2.7 ~ 3.6V
FUNCTIONAL BLOCK DIAGRAM
Vcc
Vss
A0-A17
DECODER
256Kx8
MEMORY ARRAY
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
CE2
WE#
OE#
CONTROL
CIRCUIT
COLUMN I/O
55nshttp://www.DataSheet4U.net/
20µA(L)/1µA(LL)
20mA
PIN DESCRIPTION
SYMBOL
A0 - A17
DQ0 – DQ7
CE#, CE2
WE#
OE#
VCC
VSS
NC
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Inputs
Write Enable Input
Output Enable Input
Power Supply
Ground
No Connection
10/February/07, v.1.0
Alliance Memory Inc.
Page 1 of 13
datasheet pdf - http://www.DataSheet4U.net/
1 page  
February 2007
Rev. 1.1
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
Address
Dout
tRC
Previous Data Valid
tAA
AS6C2008
®
256K X 8 BIT LOW POWER CMOS SRAM
tOH
Data Valid
READ CYCLE 2 (CE# and CE2 and OE# Controlled) (1,3,4,5)
Address
CE#
CE2
tRC
tAA
tACE
OE#
Dout
High-Z
tOLZ
tCLZ
tOE
http://www.DataSheet4U.net/
tOH
tOHZ
tCHZ
Data Valid
High-Z
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low., CE2 = high.
3.Address must be valid prior to or coincident with CE# = low, CE2 = high; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
10/February/07, v.1.0
Alliance Memory Inc.
Page 5 of 13
datasheet pdf - http://www.DataSheet4U.net/
5 Page 
February 2007
Rev. 1.1
AS6C2008
®
256K X 8 BIT LOW POWER CMOS SRAM
36 ball 6mm × 8mm TFBGA Package Outline Dimension
http://www.DataSheet4U.net/
10/February/07, v.1.0
Alliance Memory Inc.
Page 11 of 13
datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AS6C2008.PDF ] | |
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