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PDF MT41K512M4 Data sheet ( Hoja de datos )
| Número de pieza | MT41K512M4 | |
| Descripción | 1.35V DDR3L SDRAM | |
| Fabricantes | Micron Technology | |
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1.35V DDR3L SDRAM
MT41K512M4 – 64 Meg x 4 x 8 banks
MT41K256M8 – 32 Meg x 8 x 8 banks
MT41K128M16 – 16 Meg x 16 x 8 banks
2Gb: x4, x8, x16 DDR3L SDRAM
Description
Description
DDR3L SDRAM (1.35V) is a low voltage version of the
DDR3 SDRAM (1.5V). Unless stated otherwise, DDR3L
SDRAM meet the functional and timing specifications
listed in the equivalent density DDR3 SDRAM data
sheet located on www.micron.com.
Features
• VDD = VDDQ = 1.35V (1.283–1.45V)
• Backward-compatible to VDD = VDDQ = 1.5V ±0.075V
• Differential bidirectional data strobe
• 8n-bit prefetch architecture
• Differential clock inputs (CK, CK#)
• 8 internal banks
• Nominal and dynamic on-die termination (ODT)
for data, strobe, and mask signals
• Programmable CAS (READ) latency (CL)
• Programmable posted CAS additive latency (AL)
• Programmable CAS (WRITE) latency (CWL)
• Fixed burst length (BL) of 8 and burst chop (BC) of 4
(via the mode register set [MRS])
• Selectable BC4 or BL8 on-the-fly (OTF)
• Self refresh mode
• TC of 0°C to +95°C
– 64ms, 8192-cycle refresh at 0°C to +85°C
– 32ms at +85°C to +95°C
• Self refresh temperature (SRT)
• Automatic self refresh (ASR)
• Write leveling
• Multipurpose register
• Output driver calibration
Options
• Configuration
– 512 Meg x 4
– 256 Meg x 8
– 128 Meg x 16
• FBGA package (Pb-free) – x4, x8
– 78-ball (8mm x 10.5mm) Rev. H, M, K
– 78-ball FBGA (9mm x 11.5mm) Rev. D
• FBGA package (Pb-free) – x16
– 96-ball FBGA (9mm x 14mm) Rev. D
– 96-ball FBGA (8mm x 14mm) Rev. K
• Timing – cycle time
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.875ns @ CL = 7 (DDR3-1066)
• Revision
Marking
512M4
256M8
128M16
DA
HX
HA
JT
-125
-15E
-187E
:D/ :H/ :K/ :
M
Table 1: Key Timing Parameters
Speed Grade
-1251, 2
-15E1
-187E
Data Rate (MT/s)
1600
1333
1066
Target tRCD-tRP-CL
11-11-11
9-9-9
7-7-7
Notes: 1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
tRCD (ns)
13.75
13.5
13.1
tRP (ns)
13.75
13.5
13.1
CL (ns)
13.75
13.5
13.1
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. G 2/12 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
Datasheet pdf - http://www.DataSheet4U.net/
1 page  
www.DataSheet.co.kr
2Gb: x4, x8, x16 DDR3L SDRAM
Ball Assignments and Descriptions
2. A comma separates the configuration; a slash defines a selectable function.
Table 3: 78-Ball FBGA – x4, x8 Ball Descriptions
Symbol
A[14:13],
A12/BC#, A11,
A10/AP,
A[9:0]
BA[2:0]
CK, CK#
CKE
CS#
DM
ODT
RAS#, CAS#, WE#
RESET#
Type
Input
Input
Input
Input
Input
Input
Input
Input
Input
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE com-
mand determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected
by BA[2:0]) or all banks (A10 HIGH). The address inputs also provide the op-code during a
LOAD MODE command. Address inputs are referenced to VREFCA. A12/BC#: When enabled
in the mode register (MR), A12 is sampled during READ and WRITE commands to deter-
mine whether burst chop (on-the-fly) will be performed (HIGH = BL8 or no burst chop,
LOW = BC4 burst chop).
Bank address inputs: BA[2:0] define the bank to which an ACTIVATE, READ, WRITE, or
PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command. BA[2:0] are referenced to
VREFCA.
Clock: CK and CK# are differential clock inputs. All address and control input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#. Out-
put data strobe (DQS, DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal cir-
cuitry and clocks on the DRAM. The specific circuitry that is enabled/disabled is depend-
ent upon the DDR3 SDRAM configuration and operating mode. Taking CKE LOW pro-
vides PRECHARGE power-down and SELF REFRESH operations (all banks idle) or active
power-down (row active in any bank). CKE is synchronous for power-down entry and exit
and for self refresh entry. CKE is asynchronous for self refresh exit. Input buffers (exclud-
ing CK, CK#, CKE, RESET#, and ODT) are disabled during power-down. Input buffers (ex-
cluding CKE and RESET#) are disabled during SELF REFRESH. CKE is referenced to
VREFCA.
Chip select: CS# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when CS# is registered HIGH. CS# provides for exter-
nal rank selection on systems with multiple ranks. CS# is considered part of the command
code. CS# is referenced to VREFCA.
Input data mask: DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH along with the input data during a write access. Although the DM
ball is input-only, the DM loading is designed to match that of the DQ and DQS balls. DM
is referenced to VREFDQ. DM has an optional use as TDQS on the x8 device.
On-die termination: ODT enables (registered HIGH) and disables (registered LOW) ter-
mination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to each of the following balls: DQ[7:0], DQS, DQS#, and DM for the
x8; DQ[3:0], DQS, DQS#, and DM for the x4. The ODT input is ignored if disabled via the
LOAD MODE command. ODT is referenced to VREFCA.
Command inputs: RAS#, CAS#, and WE# (along with CS#) define the command being
entered and are referenced to VREFCA.
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input
receiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDDQ and DC
LOW ≤ 0.2 × VDDQ. RESET# assertion and deassertion are asynchronous.
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. G 2/12 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/
5 Page 
www.DataSheet.co.kr
2Gb: x4, x8, x16 DDR3L SDRAM
Package Dimensions
Figure 5: 96-Ball FBGA – x16; Die Rev. D (HA)
0.155
96X Ø0.45
Dimensions
apply to solder
balls post-reflow
on Ø0.35 SMD
ball pads.
1.8 CTR
Nonconductive
overmold
987
321
12 CTR
0.8 TYP
Seating plane
A 0.12 A
Ball A1 Index
(covered by SR)
A
B
C
D
E
F
G
H
J
14 ±0.1
K
L
M
N
P
R
T
Ball A1 Index
0.8 TYP
6.4 CTR
9 ±0.1
1.1 ±0.1
0.25 MIN
Note: 1. All dimensions are in millimeters.
PDF: 09005aef83ed2952
2Gb_1_35V_DDR3L.pdf - Rev. G 2/12 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Datasheet pdf - http://www.DataSheet4U.net/
11 Page | ||
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