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PDF MT41K512M16 Data sheet ( Hoja de datos )
| Número de pieza | MT41K512M16 | |
| Descripción | 32 Meg x 16 x 8 Banks 1.35V DDR3L-RS SDRAM | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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8Gb: x16 TwinDie DDR3L-RS SDRAM
Description
TwinDie™ 1.35V DDR3L-RS SDRAM
MT41K512M16 – 32 Meg x 16 x 8 Banks
Description
The 8Gb (TwinDie™) 1.35V DDR3L-RS SDRAM is a
low-current self refresh version, via a TCSR feature, of
the 1.35V DDR3L SDRAM device. It uses two Micron
4Gb DDR3L-RS SDRAM x16 die for essentially two
ranks of 4Gb DDR3L-RS SDRAM. Unless stated other-
wise, the DDR3L-RS meets the functional and timing
specifications listed in the equivalent density DDR3L
SDRAM data sheets. Refer to Micron’s 4Gb DDR3L
SDRAM data sheet for the specifications not included
in this document. Specifications for base part number
MT41K256M16 (monolithic) correlate to manufactur-
ing part number MT41K512M16.
Features
• Uses two 4Gb x16 Micron die in one package
• Two ranks (includes dual CS#, ODT, CKE and ZQ
balls)
• VDD = VDDQ = 1.35V (1.283–1.425V); backward com-
patible to 1.5V operation
• 1.35V center-terminated push/pull I/O
• JEDEC-standard ball-out
• Low-profile package
• TC of 0°C to 95°C
– 0°C to 85°C: 8192 refresh cycles in 64ms
– 85°C to 95°C: 8192 refresh cycles in 32ms
• Temperature-compensated self refresh (TCSR)
mode
• Very low-current self refresh mode when TC < 45°C
Options
• Configuration
– 32 Meg x 16 x 8 banks x 2 ranks
• FBGA package (Pb-free)
– 96-ball FBGA
(10mm x 14mm x 1.2mm) Rev. E
• Timing – cycle time1
– 1.25ns @ CL = 11 (DDR3L-1600)
– 1.5ns @ CL = 9 (DDR3L-1333)
– 1.87ns @ CL = 7 (DDR3L-1066)
• Power saving
– TCSR
• Operating temperature
– Commercial (0°C ≤ TC ≤ 95°C)
– Industrial (-40°C ≤ TC ≤ 95°C)
• Revision
Note: 1. CL = CAS (READ) latency.
Marking
512M16
TNA
-125
-15E
-187E
M
None
IT
:E
Table 1: Key Timing Parameters
Speed Grade
-1251, 2
-15E1
-187E
Data Rate (MT/s)
1600
1333
1066
Target tRCD-tRP-CL
11-11-11
9-9-9
7-7-7
Notes: 1. Backward compatible to 1066, CL = 7 (-187E).
2. Backward compatible to 1333, CL = 9 (-15E).
tRCD (ns)
13.75
13.5
13.1
tRP (ns)
13.75
13.5
13.1
CL (ns)
13.75
13.5
13.1
PDF: 09005aef84ccb511
DDR3L-RS_8Gb_x16_2CS_TwinDie.pdf - Rev. D 05/13 EN
1 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
http://www.Datasheet4U.com
1 page  
8Gb: x16 TwinDie DDR3L-RS SDRAM
Ball Assignments and Descriptions
Table 3: 96-Ball FBGA – x16 Ball Descriptions (Continued)
Symbol
RESET#
UDM
DQ[7:0]
DQ[15:8]
LDQS, LDQS#
UDQS, UDQS#
VDD
VDDQ
VREFCA
VREFDQ
VSS
VSSQ
ZQ[1:0]
NC
Type
Input
Input
I/O
I/O
I/O
I/O
Supply
Supply
Supply
Supply
Supply
Supply
Reference
–
Description
Reset: RESET# is an active LOW CMOS input referenced to VSS. The RESET# input re-
ceiver is a CMOS input defined as a rail-to-rail signal with DC HIGH ≥ 0.8 × VDD and
DC LOW ≤ 0.2 × VDDQ. RESET# assertion and de-assertion are asynchronous.
Input data mask: UDM is an upper-byte input mask signal for write data. Upper-
byte input data is masked when UDM is sampled HIGH along with that input data
during a WRITE access. Although the UDM ball is input-only, the UDM loading is
designed to match that of the DQ and DQS balls. UDM is referenced to VREFDQ.
Data input/output: Lower byte of bidirectional data bus for the x16 configuration.
DQ[7:0] are referenced to VREFDQ.
Data input/output: Upper byte of bidirectional data bus for the x16 configuration.
DQ[15:8] are referenced to VREFDQ.
Lower byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. Center-aligned to write data.
Upper byte data strobe: Output with read data. Edge-aligned with read data.
Input with write data. DQS is center-aligned to write data.
Power supply: 1.35V, 1.283–1.45V.
DQ power supply: 1.35V, 1.283–1.45V.
Reference voltage for control, command, and address: VREFCA must be
maintained at all times (including self refresh) for proper device operation.
Reference voltage for data: VREFDQ must be maintained at all times (excluding self
refresh) for proper device operation.
Ground.
DQ ground: Isolated on the device for improved noise immunity.
External reference ball for output drive calibration: This lower byte ball is tied
to an external 240Ω resistor (RZQ), which is tied to VSSQ.
No connect: These balls should be left unconnected (the ball has no connection to
the DRAM or to other balls).
PDF: 09005aef84ccb511
DDR3L-RS_8Gb_x16_2CS_TwinDie.pdf - Rev. D 05/13 EN
5 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
5 Page 
8Gb: x16 TwinDie DDR3L-RS SDRAM
Electrical Specifications – ICDD Parameters
Electrical Specifications – ICDD Parameters
Table 7: DDR3L-RSCDD Specifications and Conditions (Rev. E)
Note 8 applies to the entire table
Combined
Individual
Symbol
Die Status
ICDD0
ICDD1
ICDD2P0 (slow exit)
ICDD2P1 (fast exit)
ICDD2Q
ICDD2N
ICDD2NT
ICDD3P
ICDD3N
ICDD4R
ICDD4W
ICDD5B
Room temperature
ICDD6
45oC ICDD6ET
Elevated temperature
ICDD6
ICDD0 =
IDD0 + IDD2P0 + 5
ICDD1 =
IDD1 + IDD2P0 + 5
ICDD2P0 =
IDD2P0 + IDD2P0
ICDD2P1 =
IDD2P1 + IDD2P0
ICDD2Q =
IDD2Q + IDD2P0
ICDD2N = IDD2N + IDD2P0
ICDD2NT = IDD2NT + IDD2P0
ICDD3P = IDD3P + IDD2P0
ICDD3N = IDD3N + IDD2P0
ICDD4R =
IDD4R + IDD2P0 + 5
ICDD4W =
IDD4W + IDD2P0 = 5
ICDD5B =
IDD5B + IDD2P0
ICDD6 = IDD6 + IDD6
ICDD6 = IDD6 + IDD6
ICDD6 = IDD6 + IDD6
Extended temperature
ICDD6ET
ICDD6ET = IDD6ET + IDD6ET
ICDD7
ICDD8
ICDD7 = IDD7 + IDD2P0 + 5
ICDD8 = 2 × IDD2P0 + 4
Bus
Width
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
x16
-187E
72
97
24
36
34
34
42
39
49
193
146
233
7.0
7.4
14
17
28
36
211
28
-15E
75
101
24
38
36
36
46
42
52
210
161
236
7.0
7.4
14
17
28
36
230
28
-125
83
104
24
42
39
38
49
45
55
244
180
243
7.0
7.4
14
17
28
36
256
28
Units
mA
Notes
1
mA 1
mA 1
mA 1
mA 1
mA 1
mA 1
mA 1
mA 1
mA 1
mA 1
mA 1
mA 2
mA 3
mA 4
mA 5
mA 6
mA 7
mA 1
mA 1
Notes:
1. TC = 85°C; SRT is disabled, ASR is disable. Value is maximum.
2. Room temperature; SRT is disabled, ASR is enabled. Value is typical.
3. TC ≤ 45°C; SRT is disabled, ASR is enabled). Value is typical.
4. TC = 80°C; SRT is disabled, ASR is enabled). Value is typical.
5. 45°C < TC ≤ 80°C; SRT is disabled, ASR is enabled. Value is maximum.
6. TC = 95°C; SRT is disabled, ASR is enabled. Value is typical.
7. 85°C < TC ≤ 95°C; SRT is disabled, ASR is enabled. Value is maximum.
8. ICDD values reflect the combined current of both individual die. IDDx represents individu-
al die values.
PDF: 09005aef84ccb511
DDR3L-RS_8Gb_x16_2CS_TwinDie.pdf - Rev. D 05/13 EN
11
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MT41K512M16.PDF ] | |
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