PDF CY25568 Data sheet ( Hoja de datos )

Número de pieza	CY25568
Descripción	Spread Spectrum Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY25568 Spread Spectrum Clock Generator Features ■ 4 to 32 MHz Input frequency range ■ 4 to 128 MHz Output frequency range ■ accepts clock, crystal and resonator Inputs ■ 1x, 2x and 4x frequency multiplication ■ Non-modulated reference frequency output ■ Center and down spread modulation ■ Low power dissipation ❐ 3.3 V = 52 mW-typ at 6 MHz ❐ 3.3 V = 60 mW-typ at 12 MHz ❐ 3.3 V = 72 mW-typ at 24 MHz ■ Power-down mode ■ Low cycle-to cycle jitter ❐ 8 MHz = 195 ps-typ ❐ 16 MHz = 175 ps-typ ❐ 32 MHz = 100 ps-typ ■ Available in 16-pin (150-mil.) SOIC package Applications ■ Printers and MFPs ■ LCD panels and monitors ■ Digital copiers ■ PDAs ■ Automotive ■ CD-ROM, VCD and DVD ■ Networking, LAN/WAN ■ Scanners ■ Modems ■ Embedded digital systems Benefits ■ Peak EMI reduction by 8 to 16dB ■ Fast time to market ■ Cost reduction Logic Block Diagram 300K XIN 1 XOUT 16 8pF 8pF VDD 13 VDD 12 VSS 3 VSS 2 REFERENCE DIVIDER PD and CP LF MODULATION CONTROL VCO COUNTER VCO INPUT DECODER LOGIC 11 FRSEL 4 5 1 5 1 4 1 0 S1 SO D1 DO PD# DIVIDER and MUX 7 REFOUT 6 SSCLK1 9 SSCLK2 8 SSCLK3 Cypress Semiconductor Corporation • 198 Champion Court wwwD.DocautamSheenett4NUu.nmebt er: 38-07111 Rev. D • San Jose, CA 95134-1709 • 408-943-2600 Revised July 18, 2011 1 page CY25568 Timing Electrical Characteristics Test Conditions: VDD=3.3 V, T=25 C, CL=15pF. Rise/Fall time at 0.4 and 2.4 V, duty cycle at 1.5 V CCJ3 Cycle-to-cycle jitter - 100 150 ps Fin=32 MHz (refer to Figure 4A) Input Frequency Range and Selection The CY25568 input frequency range is 4 to 32 MHz. This range is divided into 3 segments and controlled by 3-Level FRSEL pin as given in Table 1. Table 1. Input Frequency Selection FRSEL 0 1 M INPUT FREQUENCY RANGE 4.0 to 8.0 MHz 8.0 to 16.0 MHz 16.0 to 32.0 MHz Output Clocks The CY25568 provides 4 separate output clocks, REFOUT, SSCLK1, SSCLK2 and SSCLK3, for use in a wide variety of applications.Each clock output is described in detail. REFOUT REFOUT is a 3.3 volt CMOS level non-modulated copy of the clock at XIN/CLKIN. SSCLK1, 2 and 3 SSCLK1, SSCLK2 and SSCLK3 are Spread Spectrum clock outputs used for the purpose of reducing EMI in digital systems. Each clock can drive separate nets with a capacitive load of up to 20 pF. The frequency function of these clock outputs are selected by using 3-Level D0 and D1 digital inputs and are given in Table 2. Table 2. Output Clocks Function Selection D0 D1 00 0M REFOUT REF REF 01 M0 MM M1 10 1M 11 REF REF REF REF REF REF REF SSCLK1 REF 1x REF REF REF REF REF 1x 1x SSCLK2 1x 2x 2x 1x REF 2x 4x 2x 2x SSCLK3 1x 2x 2x 2x REF 4x 4x 4x 4x REF is the same non-modulated frequency as the input clock. 1x, 2x, or 4x are modulated and multiplied (in the case of 2x and 4x) frequency of the input clock. Document Number: 38-07111 Rev. D Page 5 of 14 5 Page Package Diagram Figure 9. 16-Pin (150-Mil) SOIC CY25568 51-85068 C Document Number: 38-07111 Rev. D Page 11 of 14 11 Page

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