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PDF CY2547 Data sheet ( Hoja de datos )
| Número de pieza | CY2547 | |
| Descripción | (CY2545 / CY2547) Quad PLL Programmable Spread Spectrum Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY2545, CY2547
Quad PLL Programmable
Spread Spectrum Clock Generator
with Serial I2C Interface
Features
■ Four fully integrated phase locked loops (PLLs)
■ Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Serial programmable over 2-wire I2C interface
■ Programmable spread spectrum with center and down spread
option and Lexmark and Linear modulation profiles
■ VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V for CY2545
❐ 1.8 V for CY2547
■ Selectable output clock voltages independent of VDD supply:
❐ 2.5 V, 3.0 V, and 3.3 V for CY2545
❐ 1.8 V for CY2547
■ Power-down, output enable, or frequency select features
■ Low jitter, high accuracy outputs
■ Ability to synthesize nonstandard frequencies with Fractional-N
capability
Logic Block Diagram
■ Up to eight clock outputs with programmable drive strength
■ Glitch-free outputs while frequency switching
■ 24-pin QFN package
■ Commercial and industrial temperature ranges
Benefits
■ Multiple high performance PLLs allow synthesis of unrelated
frequencies
■ Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■ Application specific programmable EMI reduction using Spread
Spectrum for clocks
■ Programmable PLLs for system frequency margin tests
■ Meets critical timing requirements in complex system designs
■ Suitability for PC, consumer, portable, and networking applica-
tions
■ Capable of zero PPM frequency synthesis error
■ Uninterrupted system operation during clock frequency switch
■ Application compatibility in standard and low power systems
CLKIN/RST
XIN/
EXCLKIN
XOUT
OSC
FS
MUX
and
Control
Logic
PLL1
PLL2
PLL3
(SS)
Crossbar
Switch
Bank
Output 1
Dividers
and
Drive Bank
2
Strength
Control
Bank
3
CLK1
CLK 2
CLK3
CLK 4
CLK 5
CLK 6
CLK 7
CLK 8
SCL
SDA
SSON
I2C
PLL4
(SS)
PD #/ OE
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-13196 Rev. *C
• San Jose, CA 95134-1709 • 408-943-2600
Revised July 5, 2011
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CY2545, CY2547
Table 2. Pin Definition – CY2547 24-pin QFN (VDD = 1.8 V Supply) (continued)
Pin Number
Name
I/O
Description
21
CLKIN/RST
Input/Input
Multifunction programmable pin: High true reset input or 1.8 V external low
voltage reference clock input
22 VDD
Power
Power supply for core and inputs: 1.8 V
23
XOUT
Output
Crystal output
24
XIN/EXCLKIN Input
Crystal input or 1.8 V external clock input
General Description
Four Configurable PLLs
The CY2545 and CY2547 have four I2C programmable PLLs
available to generate output frequencies ranging from 3 to 166
MHz. The advantage of having four PLLs is that a single device
generates up to four independent frequencies from a single
crystal. Two sets of frequencies for each PLL can be
programmed. This enables in system frequency switching using
multifunction frequency select pin, FS.
I2C Programming
The CY2545 and CY2547 have a serial I2C interface that
programs the configuration memory array to synthesize output
frequencies by programmable output divider, spread character-
istics, drive strength, and crystal load capacitance. I2C can also
be used for in system control of these programmable features.
Input Reference Clocks
The input to the CY2545 and CY2547 is either a crystal or a clock
signal. The input frequency range for crystals is 8 MHz to 48
MHz. There is provision for two reference clock inputs, CLKIN
and EXCLKIN with frequency range of 8 MHz to 166 MHz. For
both devices, when CLKIN signal at pin 21 is used as a reference
input, a valid signal at EXCLKIN (as specified in the AC and DC
Electrical Specification table), must be present for the devices to
operate properly.
Multiple Power Supplies
The CY2545 and CY2547 are designed to operate at internal
core supply voltage of 1.8 V. In the case of the high voltage part
(CY2545), an internal regulator is used to generate 1.8 V from
the 2.5 V/3.0 V/3.3 V VDD supply voltage at pin 22. For the low
voltage part (CY2547), this internal regulator is bypassed and 1.8
V at VDD pin 22 is directly used.
Output Bank Settings
These devices have eight clock outputs grouped in three output
driver banks. The Bank 1, Bank 2, and Bank 3 correspond to
(CLK1, CLK2), (CLK3, CLK4, CLK5), and (CLK6, CLK7, CLK8),
respectively. Separate power supplies are used for each of these
banks and they can be any of 2.5 V, 3.0 V, or 3.3 V for CY2545
and 1.8 V for CY2547 giving user multiple choice of output clock
voltage levels.
Output Source Selection
These devices have eight clock outputs (CLK1 - 8). There are six
available clock sources for these outputs. These clock sources
are: XIN/EXCLKIN, CLKIN, PLL1, PLL2, PLL3, or PLL4. Output
clock source selection is done using four out of six crossbar
switch. Thus, any one of these six available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have up to four independent clock outputs.
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and Spread Spectrum Clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Frequency Select
The device can store two different PLL frequency configurations,
output source selection and output divider values for all eight
outputs in its nonvolatile memory location. There is a multi-
function programmable pin, CLK3/FS which, if programmed as
frequency select input, can be used to select between these two
arbitrarily programmed settings.
Glitch-Free Frequency Switch
When the frequency select pin (FS) is used to switch frequency,
the outputs are glitch-free provided frequency is switched using
output dividers. This feature enables uninterrupted system
operation while clock frequency is switched.
Device Reset Function
There is a multifunction CLKIN/RST (pin 21) that can be
programmed to use for the device reset function. There are two
different programmable modes of operation for this device reset
function. First one (called POR like reset), when used brings the
device in the default register settings loosing all configuration
changes made through the I2C interface. The second (called
Clean Start), keeps the I2C programmed values while giving all
outputs a simultaneous clean start from its low pull-down state.
Document #: 001-13196 Rev. *C
Page 5 of 17
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CY2545, CY2547
DC Electrical Specifications
Parameter
Description
Conditions
Min Typ Max Unit
VOL
VOH
VOLSD
VIL1
Output low voltage
IOL = 2 mA, drive strength = [00]
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
Output high voltage
IOH = –2 mA, drive strength = [00]
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
Output low voltage, SDA
IOL = 4 mA
Input low voltage of PD#/OE, RST,
FS, and SSON
– – 0.4 V
VDD_CLK_BX
– 0.4
–
–V
– – 0.4 V
– – 0.2 × VDD V
VIL2 Input low voltage of CLKIN for
CY2545
– – 0.1 × VDD V
VIL3 Input low voltage of EXCLKIN for
CY2545
– – 0.18 V
VIL4 Input low voltage of CLKIN,
EXCLKIN for CY2547
– – 0.1 × VDD V
VIH1
Input high voltage of PD#/OE,
RST, FS, and SSON
0.8 × VDD –
–V
VIH2 Input high voltage of CLKIN for
CY2545
0.9 × VDD –
–V
VIH3 Input high voltage of EXCLKIN for
CY2545
1.62 – 2.2 V
VIH4 Input high voltage of CLKIN,
EXCLKIN for CY2547
0.9 × VDD –
–V
IILPD
Input low current of RST and
PD#/OE
VIL = 0 V
– – 10 µA
IIHPD
Input high current of RST and
PD#/OE
VIH = VDD
– – 10 µA
IILSR
IIHSR
RDN
IDD[1, 2]
IDDS[1]
IPD[1]
CIN[1]
Input low current of SSON and FS VIL = 0 V (Internal pull-down = 160 k typ)
Input high current of SSON and FS VIH = VDD (Internal pull-down = 160 k typ)
Pull-down resistor of (CLK1-CLK8)
when off, CLK6/SSON and
CLK3/FS
Supply current for CY2547
PD# = high, no load
Supply current for CY2545
Standby current
Power-down current
PD# = high, no load
PD# = low, no load, with I2C circuit not in
keep alive mode
PD# = low, no load, with I2C circuit in keep
alive mode
Input capacitance
SSON, RST, PD#/OE or FS inputs
–
14
100
–
–
–
–
–
– 10 µA
– 36 µA
160 250 kΩ
20 – mA
22 – mA
3 – µA
– 1 mA
7 pF
Notes
1. Guaranteed by design but not 100% tested.
2. Configuration dependent.
Document #: 001-13196 Rev. *C
Page 11 of 17
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| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet CY2547.PDF ] | |
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