PDF CY25404 Data sheet ( Hoja de datos )

Número de pieza	CY25404
Descripción	Quad PLL Programmable Clock Generator
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY25404 Quad PLL Programmable Clock Generator with Spread Spectrum Features ■ Four fully integrated phase-locked loops (PLLs) ■ Input frequency range ❐ External crystal: 8 to 48 MHz ❐ External reference: 8 to 166 MHz clock ■ Wide operating output frequency range ❐ 3 to 166 MHz ■ Programmable spread spectrum with center and down spread option and lexmark and linear modulation profiles ■ Selectable VDD supply voltage options: ❐ 2.5 V, 3.0 V, and 3.3 V ■ Selectable output clock voltages, independent of VDD supply: ❐ 2.5 V, 3.0 V, and 3.3 V ■ Frequency select feature with option to select eight different frequencies over nine clock outputs ■ Output enable, and SS ON/OFF controls ■ Low jitter, high accuracy outputs ■ Ability to synthesize nonstandard frequencies with Fractional-N capability ■ Up to nine clock outputs with programmable drive strength ■ Glitch-free outputs while frequency switching ■ 20-pin TSSOP package ■ Commercial and Industrial temperature ranges Benefits ■ Multiple high performance PLLs allow synthesis of unrelated frequencies ■ Nonvolatile programming for personalization of PLL frequencies, spread spectrum characteristics, drive strength, crystal load capacitance, and output frequencies ■ Application specific programmable electromagnetic interference (EMI) reduction using spread spectrum for clocks ■ Programmable PLLs for system frequency margin tests ■ Meets critical timing requirements in complex system designs ■ Suitability for PC, consumer, portable, and networking applications ■ Capable of zero parts per million (PPM) frequency synthesis error ■ Uninterrupted system operation during clock frequency switch ■ Application compatibility in standard and low power systems Block Diagram XIN/ EXCLKIN XOUT OSC FS 0 FS 1 FS 2 MUX and Control Logic SSON PLL1 PLL2 PLL3 (SS) PLL4 (SS) Crossbar Switch Bank 1 Output Dividers and Bank 2 Drive Strength Control Bank 3 CLK1 CLK2 CLK3 CLK4 CLK5 CLK6 CLK7 CLK8 CLK9 OE Cypress Semiconductor Corporation • 198 Champion Court wwwD.DocautamSheenett4#U: .0n0et1-43258 Rev. C • San Jose, CA 95134-1709 • 408-943-2600 Revised July 11, 2011 1 page CY25404 Absolute Maximum Conditions Parameter VDD VDD_CLK_BX VIN TS ESDHBM UL-94 MSL Description Supply voltage Output bank supply voltage Input voltage Temperature, storage ESD protection (human body model) Flammability rating Moisture sensitivity level Condition – – Relative to VSS Non functional JEDEC EIA/JESD22-A114-E V-0 at 1/8 in. – Min –0.5 –0.5 –0.5 –65 2000 – Max 4.5 4.5 VDD+0.5 +150 10 3 Unit V V V °C volts ppm Recommended Operating Conditions Parameter Description Min Typ Max Unit VDD VDD operating voltage 2.25 – 3.60 V VDD_CLK_BX Output driver voltage for Bank 1, 2 and 3 2.25 – 3.60 V TAC Commercial ambient temperature 0 – +70 °C TAI Industrial ambient temperature –40 -- +85 °C CLOAD Maximum load capacitance – – 15 pF tPU Power-up time for all VDD to reach minimum specified voltage (power ramps must 0.05 – 500 ms be monotonic) Notes 1. Guaranteed by design but not 100% tested. 2. Configuration dependent. Document #: 001-43258 Rev. C Page 5 of 13 5 Page Acronyms Acronym DL EMI ESD FAE FS JEDEC EIA OE OSC PD PLL PPM SS SSC SSON TSSOP Description drive level electromagnetic interference electrostatic discharge field application engineer frequency select joint electron devices engineering council electronic industries alliance output enable oscillator power-down phase-locked loop parts per million spread spectrum spread spectrum clock spread spectrum on thin shrunk small outline package Document Conventions Units of Measure Symbol °C fF mA MHz s ms W ns pF ppm ps V  W Unit of Measure degrees Celsius femtofarads milliampere megahertz microseconds millisecond microwatts nanoseconds picofarads parts per million picoseconds volts ohms watts Document #: 001-43258 Rev. *C CY25404 Page 11 of 13 11 Page

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