|
|
PDF CY25402 Data sheet ( Hoja de datos )
| Número de pieza | CY25402 | |
| Descripción | (CY25402 - CY25482) Two PLL Programmable Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CY25402 (archivo pdf) en la parte inferior de esta página. Total 14 Páginas | ||
|
No Preview Available !
CY25402/CY25422/CY25482
Two PLL Programmable Clock Generator
with Spread Spectrum
Features
■ Two fully integrated phase locked loops (PLLs)
■ Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
■ Reference clock input voltage range
❐ 2.5 V, 3.0 V, and 3.3 V for CY25482
❐ 1.8 V for CY25402 and CY25422
■ Wide operating output frequency range
❐ 3 to 166 MHz
■ Programmable spread spectrum with center and down spread
option and lexmark and linear modulation profiles
■ VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐ 1.8 V for CY25422
■ Selectable output clock voltages independent of VDD:
❐ 2.5 V, 3.0 V, and 3.3 V for CY25402 and CY25482
❐ 1.8 V for CY25422
■ Frequency select feature with option to select four different
frequencies
■ Power-down, Output Enable, and SS ON/OFF controls
■ Low jitter, high accuracy outputs
Block Diagram
■ Ability to synthesize nonstandard frequencies with Fractional-N
capability
■ Three clock outputs with programmable drive strength
■ Glitch-free outputs while frequency switching
■ 8-pin small outline integrated circuit (SOIC) package
■ Commercial and Industrial temperature ranges
Benefits
■ Multiple high performance PLLs allow synthesis of unrelated
frequencies
■ Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■ Application specific programmable EMI reduction using spread
spectrum for clocks
■ Programmable PLLs for system frequency margin tests
■ Meets critical timing requirements in complex system designs
■ Suitability for PC, consumer, portable, and networking
applications
■ Capable of zero parts per million (PPM) frequency synthesis
error
■ Uninterrupted system operation during clock frequency switch
■ Application compatibility in standard and low power systems
XIN/
EXCLKIN
XOUT
OSC
FS0
FS1
MUX
and
Control
Logic
PLL 1
(SS)
PLL 2
(SS)
Crossbar
Switch
Output
Dividers
and
Drive
Strength
Control
CLK1
REFOUT
CLK2
SSON
PD#/OE
Cypress Semiconductor Corporation • 198 Champion Court
wwwD.DocautamSheenett4#U: .0n0et1-12565 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 20, 2011
1 page  
CY25402/CY25422/CY25482
General Description
2 Configurable PLLs
The CY25402, CY25422, and CY25482 have two programmable
PLLs that can be used to generate output frequencies ranging
from 3 to 166 MHz. The advantage of having two PLLs is that a
single device generates two independent frequencies from a
single crystal.
Input Reference Clocks
The input reference clock can be either a crystal or a clock signal,
for CY25402 and CY25422 while just a clock signal for CY25482.
The input frequency range for crystal (XIN) is 8 MHz to 48 MHz
and that for external reference clock (EXCLKIN) is 8 MHz to 166
MHz. The voltage range of the reference clock input for CY25482
is 2.5 V/3.0 V/3.3 V while that for CY25402 and CY25422 is
1.8 V. This gives user an option for this device to be compatible
for different input clock voltage levels in the system.
VDD Power Supply Options
These devices have programmable power supply options. The
CY25402/CY25482 is a high voltage part that can be
programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V while
CY25422 is a low voltage part that can operate at 1.8 V.
Output Source Selection
These devices have programmable input sources for each of its
clock outputs. There are three available clock sources and these
clock sources are: XIN/EXCLKIN, PLL1, and PLL2. Output clock
source selection is done by using three out of three crossbar
switch. Thus, any one of these three available clock sources can
be arbitrarily selected for the clock outputs. This gives user a
flexibility to have two independent clock outputs.
Spread Spectrum Control
Both PLLs (PLL1 and PLL2) have spread spectrum capability for
EMI reduction in the system. The device uses a Cypress
proprietary PLL and spread spectrum clock (SSC) technology to
synthesize and modulate the frequency of the PLL. The spread
spectrum feature can be turned on or off using a multifunction
control pin (CLK2/SSON). It can be programmed to either center
spread range from ±0.125% to ±2.50% or down spread range
from –0.25% to –5.0% with lexmark or linear profile.
Frequency Select
Each PLL can be programmed for up to four different
frequencies. There are two multifunction programmable pins,
REFOUT/FS0 and PD#/OE/FS1 which if programmed as
frequency select inputs, can be used to select among these
arbitrarily programmed frequency settings. Each output has
programmable output divider options.
Glitch-Free Frequency Switch
When the frequency select pin, FS(1:0) is used to switch
frequency, the outputs are glitch-free provided frequency is
switched using output dividers. This feature enables
uninterrupted system operation while clock frequency is being
switched.
PD#/OE Mode
Multifunction pin PD#/OE/FS1 (Pin 5) can be programmed to
operate as either frequency select (FS1), power down (PD#) or
output enable (OE) mode. PD# is a low-true input. If activated it
shuts off the entire chip, resulting in minimum power
consumption for the device. Setting this signal high brings the
device in the operational mode with default register settings.
When this pin is programmed as Output Enable (OE), clock
outputs can be enabled or disabled using OE (pin 5). Individual
clock outputs can be programmed to be sensitive to this OE pin.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 4 on page 4 shows the
typical rise and fall times for different drive strength settings.
Table 5. Output Drive Strength
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Low 6.8
Mid Low
3.4
Mid High
2.0
High
1.0
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
devices, CY25402, CY25422, and CY25482 can be custom
programmed to any desired frequencies and listed features. For
customer specific programming, please contact local Cypress
field application engineer (FAE) or sales representative.
Document #: 001-12565 Rev. *F
Page 5 of 14
5 Page 
CY25402/CY25422/CY25482
Ordering Code Definitions
CY254x2 SX C/I - xxx T
Package Type: (T = Tape and Reel)
Customer specific identification code
Temperature code (C=Commercial or I=Industrial)
8-Pin SOIC package
Marketing Code: CY25402/22/82 = Device Number
Package Drawing and Dimensions
Figure 7. 8-Pin (150-Mil) SOIC S8
Document #: 001-12565 Rev. *F
51-85066 *D
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet CY25402.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CY25402 | (CY25402 - CY25482) Two PLL Programmable Clock Generator | Cypress Semiconductor |
| CY25403 | (CY254x3) Three PLL Programmable Clock Generator | Cypress Semiconductor |
| CY25404 | Quad PLL Programmable Clock Generator | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |