PDF CY2510 Data sheet ( Hoja de datos )

Número de pieza	CY2510
Descripción	(CY2509 / CY2510) Ten/Eleven Output Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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CY2509/10 Spread Aware™, Ten/Eleven Output Zero Delay Buffer Features www.D■ataSfSrhepeqreeut4aeUdn.ncAeytwtaimrein™g designed to work with spread generator (SSFTG) reference spectrum signals ■ Well suited to both 100- and 133-MHz designs Ten (CY2509) or eleven (CY2510) low-voltage complementary metal oxide semiconductor (LVCMOS) / low-voltage transistor- transistor logic (LVTTL) outputs. ■ 50 ps typical peak cycle-to-cycle jitter ■ Single output enable pin for CY2510 version, dual pins on CY2509 devices allow shutting down a portion of the outputs ■ 3.3 V power supply ■ On-chip 25  damping resistors ■ Available in 24-pin thin shrunk small outline package (TSSOP) package ■ Improved tracking skew, but narrower frequency support limit when compared to W132-09B/10B Block Diagram Key Specifications Operating voltage: ...............................................3.3 V±10% Operating range: ......................... 40 MHz < fOUT < 140 MHz Cycle-to-cycle jitter: ................................................. <100 ps Output to output skew: ............................................. <100 ps Phase error jitter: ...................................................... <100 ps FBIN CLK PLL OE0:4 OE OE5:8 FBOUT Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Configuration of these blocks dependent upon specific option being used Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-07230 Rev. E • San Jose, CA 95134-1709 • 408-943-2600 Revised July 5, 2011 1 page CY2509/10 VDD VDD Figure 1. CY2510 Example Schematic 1 AGND CLK 24 2 VDD 0.1F 3 Q0 4 Q1 5 Q2 6 GND AVDD23 VDD 22 0.1F Q9 21 Q8 20 GND 19 0.1F FB 3.3V 10F 10F FB VDD 7 GND GND 18 8 Q3 Q7 17 9 Q4 Q6 16 10 VDD 0.1F 11 OE Q5 15 VDD 14 12 FBOUT FBIN 13 0.1F VDD Spread Aware™ Many systems being designed now utilize a technology called Spread Spectrum Frequency Timing Generation. Cypress has been one of the pioneers of SSFTG development, and we designed this product so as not to filter off the Spread Spectrum feature of the Reference input, assuming it exists. When a zero delay buffer is not designed to pass the SS feature through, the result is a significant amount of tracking skew which may cause problems in systems requiring synchronization. For more details on Spread Spectrum timing technology, please see the Cypress application note titled, “EMI Suppression Techniques with SSFTG ICs.” How to Implement Zero Delay Typically, Zero Delay Buffers (ZDBs) are used because a designer wants to provide multiple copies of a clock signal in phase with each other. The whole concept behind ZDBs is that the signals at the destination chips are all going HIGH at the same time as the input to the ZDB. In order to achieve this, layout must compensate for trace length between the ZDB and the target devices. The method of compensation is described below. External feedback is the trait that allows for this compensation. Since the PLL on the ZDB will cause the feedback signal to be in phase with the reference signal. When laying out the board, match the trace lengths between the output being used for feed back and the FBIN input to the PLL. If it is desirable to either add a little delay, or slightly precede the input signal, this may also be affected by either making the trace to the FBIN pin a little shorter or a little longer than the traces to the devices being clocked. Inserting Other Devices in Feedback Path Another nice feature available due to the external feedback is the ability to synchronize signals up to the signal coming from some other device. This implementation can be applied to any device (ASIC, multiple output clock buffer/driver, etc.) which is put into the feedback path. Referring to Figure 2, if the traces between the ASIC/buffer and the destination of the clock signal(s) (A) are equal in length to the trace between the buffer and the FBIN pin, the signals at the destination(s) device will be driven HIGH at the same time the Reference clock provided to the ZDB goes HIGH. Synchronizing the other outputs of the ZDB to the outputs form the ASIC/Buffer is more complex however, as any propagation delay in the ASIC/Buffer must be accounted for. Figure 2. Additional Buffering Feedback Path Example Schematic Reference Signal Feedback Input Zero Delay Buffer ASIC/ Buffer A Document Number: 38-07230 Rev. E Page 5 of 11 5 Page CY2509/10 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 \| PSoC 3 \| PSoC 5 © Cypress Semiconductor Corporation, 2010-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-07230 Rev. *E Revised July 5, 2011 Page 11 of 11 11 Page

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