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PDF CY25100 Data sheet ( Hoja de datos )
| Número de pieza | CY25100 | |
| Descripción | Field and Factory Programmable Spread Spectrum Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY25100
Field and Factory Programmable
Spread Spectrum Clock Generator for EMI Reduction
Field and Factory Programmable Spread Spectrum Clock Generator for EMI Reduction
Features
■ Wide Operating Output (SSCLK) Frequency Range
❐ 3 MHz to 200 MHz
■ Programmable Spread Spectrum with nominal 31.5 kHz
Modulation Frequency
❐ Center Spread: ±0.25% to ±2.5%
❐ Down Spread: –0.5% to –5.0%
■ Input frequency range
❐ External Crystal: 8 to 30 MHz Fundamental Crystals
❐ External Reference: 8 to 166 MHz Clock
■ Integrated Phase-Locked Loop (PLL)
■ Field Programmable devices available
■ Programmable Crystal Load Capacitor Tuning Array
■ Low Cycle-to-cycle Jitter
■ Spread Spectrum on/off function
■ Powerdown or Output Enable function
■ Commercial and Industrial temperature ranges
■ 3.3 V operation
■ 8-pin TSSOP and SOIC packages
Functional Description
The CY25100 is a Spread Spectrum Clock Generator (SSCG) IC
used to reduce EMI found in today’s high speed digital electronic
systems.
The device uses a Cypress proprietary PLL and Spread
Spectrum Clock (SSC) technology to synthesize and modulate
the frequency of the input clock. By frequency modulating the
clock, the measured EMI at the fundamental and harmonic
frequencies are greatly reduced. This reduction in radiated
energy can significantly reduce the cost of complying with
regulatory agency (EMC) requirements and improve
time-to-market without degrading system performance.
The CY25100 uses a factory or field-programmable
configuration memory array to synthesize output frequency,
spread percentage, crystal load capacitor, reference clock output
on/off, spread spectrum on/off function, and PD#/OE options.
The spread percentage is programmed to either center spread
or down spread with various spread percentages. The range for
center spread is from ±0.25% to ±2.50%. The range for down
spread is from –0.5% to –5.0%.
The input to the CY25100 can either be a crystal or a clock
signal. The CY25100 has two clock outputs: REFCLK and
SSCLK. The non-spread spectrum REFCLK output has the
same frequency as the input of the CY25100.
For a complete list of related documentation, click here.
Logic Block Diagram
RFB
3
XIN
2
XOUT
4
PD# or OE
8
SSON#
C X IN
CXOUT
PLL
w ith
M O D U L A T IO N
CONTROL
PROGRAMMABLE
C O N F IG U R A T IO N
OUTPUT
DIVIDERS
and
MUX
6
REFCLK
7
SSCLK
1
VDD
5
VSS
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-07499 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 10, 2016
1 page  
CY25100
Absolute Maximum Ratings
Supply Voltage (VDD) ...................................... –0.5 to +7.0 V
DC Input Voltage ................................ –0.5 V to VDD + 0.5 V
Storage Temperature
(Non condensing) .................................... –55 C to +125 C
Junction Temperature .............................. –40 C to +125 C
Data Retention at Tj = 125 C ..............................> 10 years
Package Power Dissipation ..................................... 350 mW
Static Discharge Voltage
(per MIL-STD-883, Method 3015) .......................... > 2000V
Recommended Crystal Specifications
Parameter
Description
Comments
Min Typ Max Unit
fNOM
Nominal Crystal Frequency
Parallel resonance, fundamental
mode, AT cut
8
– 30 MHz
CLNOM
R1
Nominal Load Capacitance
Equivalent Series Resistance
(ESR)
Internal load caps
Fundamental mode
6 – 30 pF
– – 25
R3/R1
Ratio of Third Overtone Mode Ratio used because typical R1
3
–
––
ESR to Fundamental Mode ESR values are much less than the
maximum spec
DL Crystal Drive Level
No external series resistor assumed
–
0.5
2 mW
Operating Conditions
Parameter
VDD
TA
CLOAD
fREF
fSSCLK
fREFCLK
fMOD
tPU
Description
Supply Voltage
Ambient Commercial Temperature
Ambient Industrial Temperature
Maximum Load Capacitance at Pin 6 and Pin 7
External Reference Crystal (Fundamental tuned crystals only)
External Reference Clock
SSCLK Output Frequency, CLOAD = 15 pF
REFCLK Output Frequency, CLOAD = 15 pF
Spread Spectrum Modulation Frequency
Power Up Time for all VDD’s to reach minimum specified voltage (power
ramp must be monotonic)
Min
3.13
0
–40
–
8
8
3
8
30.0
0.05
Typ
3.30
–
–
–
–
–
–
–
31.5
–
Max Unit
3.45 V
70 °C
85 °C
15 pF
30 MHz
166 MHz
200 MHz
166 MHz
33.0 kHz
500 ms
Document Number: 38-07499 Rev. *L
Page 5 of 18
5 Page 
Informational Graphs (continued)
The Informational Graphs are as follows. [8]
Measured Spread% vs. VDD over Tem perature
(Target Spread = 0.5%, Fout=100MHz, CLOAD=15pF)
0.60%
0.55%
0.50%
0.45%
0.40%
2.7
3 3.3 3.6
VDD (V)
3.9
-40C
25C
85C
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=0.5%, CLOAD=15pF)
0
-2
-4
-6
-8
-10
2.7
3 3.3 3.6
VDD (V)
3.9
-40C
25C
85C
SSCLK EMI Attenuation vs. Spread%
(Measured at 7th Harmonic Temp=25C, VDD=3.3V,
SSCLK=100MHz, Measured on Cypress
Characterization board w ith CLOAD=15pF)
0
-2
-4
-6
-8
- 10
- 12
- 14
- 16
0.0%
0.5%
1.0%
1.5%
2.0% 2.5% 3.0%
Spread %
3.5%
4.0%
4.5%
5.0%
CY25100
Measured Spread% vs. VDD over
Tem perature
(Target Spread = 5.0%, Fout=100MHz, CLOAD=15pF)
6.00%
5.50%
5.00%
4.50%
4.00%
2.7
3 3.3 3.6
VDD (V)
3.9
-40C
25C
85C
SSCLK Attenuation vs. VDD over Tem perature
(Measured at 7th Harmonic w ith Fnom=100MHz and
Spread=5.0%, CLOAD=15pF)
-10
-12
-14
-16
-18
-20
2.7
3 3.3 3.6
VDD (V)
3.9
-40C
25C
85C
Max Cycle-Cycle Jitter on SSCLK vs.
Tem perature
(SSCLK=100MHz, VDD=3.3V, CLOAD=15pF, +/-
2%spread, REFCLK off)
200
175
150
125
100
75
50
25
0
-40 -20 0 20 40 60
Tem perature (deg C)
80 100
Document Number: 38-07499 Rev. *L
Page 11 of 18
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet CY25100.PDF ] | |
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