PDF ADAU1373 Data sheet ( Hoja de datos )

Número de pieza	ADAU1373
Descripción	Low Power Codec
Fabricantes	Analog Devices
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No Preview Available ! www.DataSheet4U.net Low Power Codec with Speaker and Headphone Amplifier ADAU1373 FEATURES 1 stereo ADC and 2 stereo DACs with sampling rates from 8 kHz to 48 kHz Low power: 7 mW record, 6 mW playback, 48 kHz at 1.8 V 8 single-ended or 4 differential inputs with PGA 2 microphone bias reference voltages with current sense 2 stereo digital microphone inputs Flexible analog input/output mixers 1 stereo differential or 2 stereo single-ended line outputs True ground-centered stereo Class-G headphone amplifier, capable of 2 × 50 mW into 16 Ω at 1.8 V, 10% THD Filterless stereo Class-D speaker amplifier, capable of 2 × 880 mW into 8 Ω at 3.6 V, 10% THD Differential earpiece amplifier capable of driving 32 Ω 2 PLLs, supporting input clocks from 8 kHz to 27 MHz I2C control interface Digital audio processing 3 digital audio input and output ports with ASRC I2S, PCM, right-justified, left-justified modes 4.05 mm × 3.82 mm, 81-ball, 0.4 mm pitch WLCSP package −40°C to +85°C operating temperature range APPLICATIONS Mobile phones, tablet PCs, e-books, portable media players GENERAL DESCRIPTION The ADAU1373 is a low power, stereo audio codec with integrated digital audio processing that supports stereo 48 kHz record and playback. The stereo audio ADCs and DACs support sampling rates from 8 kHz to 48 kHz, as well as a digital volume control. Eight single-ended or four differential analog inputs with PGAs are provided for adjusting the gain from −12 dB to +18 dB. They can be configured for microphones or line level signals. Two stereo digital microphone inputs are supported; four digital microphones can be connected in total. In addition, three serial digital audio input/output ports are provided with asynchronous sample rate converters (ASRCs) to support various sampling rates, allowing for flexible system design in mobile phone applications. The inputs can be mixed and selected before the ADC or con- figured to bypass the ADC. Two stereo DACs are included, with a flexible mixing option for routing the signals internally. The analog output side consists of line outputs, headphone output, speaker output, and receiver output. Two stereo single-ended line level outputs, which can be configured as two differential outputs, are included. The headphone output is stereo true ground centered (eliminating the need for coupling capacitors), with efficient Class-G (rail switching) architecture. The efficient stereo filterless Class-D switching amplifier provides ~1 W of stereo power for speakers. The differential receiver amplifier can be used to connect the separate receiver speaker. Two PLL blocks, which can lock to the inputs from 8 kHz to 27 MHz, are included. The DSP allows system designers to compensate for the real-world limitations of microphones, speakers, amplifiers, and listening environments, resulting in a dramatic improvement in perceived audio quality through equalization, multiband compression, and limiting algorithms. The SigmaStudio™ graphical development tool, which includes audio processing blocks such as filters, mixers, dynamics processors, and amplifiers for fast development of custom signal flows, is used to program the ADAU1373. FUNCTIONAL BLOCK DIAGRAM BCLKA/BCLKB/BCLKC LRCLKA/LRCLKB/LRCLKC SDATAINA/SDATAINB/SDATAINC SDATAOUTA/SDATAOUTB/SDATAOUTC DMIC1_2_DATA DMIC3_4_DATA DMIC_CLK MICBIAS1, MICBIAS2 AIN1L/AIN1P TO AIN4L/AIN4P AIN1R/AIN1N TO AIN4R/AIN4N SERIAL DIGITAL AUDIO INTERFACE A DIGITAL MICROPHONE MUX MIX ANALOG PLLA INPUTS INPUT OUTPUT MUX ADC I2C EARPIECE AMP FDSP LINEOUT2 LINEOUT1 DAC1 DAC2 GPIO MUX MIX HEADPHONE AMP SPEAKER AMP EPP EPN LOUT1L/LOUTLP, LOUT2L/LOUTLN LOUT1R/LOUTRP, LOUT2R/LOUTRN LN1FBIN, LN2FBIN HPL SGND HPR SPKLP SPKLN SPKRP SPKRN Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved. 1 page ADAU1373 FDSP_SEL2 Register................................................................ 253 FDSP_SEL3 Register................................................................ 254 FDSP_SEL4 Register................................................................ 255 PBALPCTRL1 Register ........................................................... 256 PBBLPCTRL2 Register............................................................ 257 DIGMICCTRL Register .......................................................... 259 GPIOSEL1 Register.................................................................. 260 GPIOSEL2 Register.................................................................. 261 IRQ_MASK Register ............................................................... 262 IRQ_RAW Register.................................................................. 263 IRQ_STATE (After Mask) Register ....................................... 264 IRQEN Register........................................................................ 265 PAD_CTRL1 Register.............................................................. 265 PAD_CTRL2 Register.............................................................. 266 DIGEN Register........................................................................ 267 LPCNTCTRL (Low Power Control Counter) Register....... 268 CHIP_ID_HI Register............................................................. 268 CHIP_ID_MID Register ......................................................... 269 CHIP_ID_LOW Register........................................................ 269 SOFT_RESET Register ............................................................ 269 Register Map—EQ Coefficients ................................................. 270 EQ1_COEF0_HI Register....................................................... 271 EQ1_COEF0_LO Register ...................................................... 271 EQ1_COEF1_HI Register....................................................... 271 EQ1_COEF1_LO Register ...................................................... 272 EQ1_COEF2_HI Register....................................................... 272 EQ1_COEF2_LO Register ...................................................... 272 EQ1_COEF3_HI Register....................................................... 273 EQ1_COEF3_LO Register ...................................................... 273 EQ1_COEF4_HI Register....................................................... 273 EQ1_COEF4_LO Register ...................................................... 274 EQ2_COEF0_HI Register....................................................... 274 EQ2_COEF0_LO Register ...................................................... 274 EQ2_COEF1_HI Register....................................................... 275 EQ2_COEF1_LO Register ...................................................... 275 EQ2_COEF2_HI Register....................................................... 275 EQ2_COEF2_LO Register ...................................................... 276 EQ2_COEF3_HI Register....................................................... 276 EQ2_COEF3_LO Register ...................................................... 276 EQ2_COEF4_HI Register....................................................... 277 EQ2_COEF4_LO Register ...................................................... 277 EQ3_COEF0_HI Register........................................................277 EQ3_COEF0_LO Register.......................................................278 EQ3_COEF1_HI Register........................................................278 EQ3_COEF1_LO Register.......................................................278 EQ3_COEF2_HI Register........................................................279 EQ3_COEF2_LO Register.......................................................279 EQ3_COEF3_HI Register........................................................279 EQ3_COEF3_LO Register.......................................................280 EQ3_COEF4_HI Register........................................................280 EQ3_COEF4_LO Register.......................................................280 EQ4_COEF0_HI Register........................................................281 EQ4_COEF0_LO Register.......................................................281 EQ4_COEF1_HI Register........................................................281 EQ4_COEF1_LO Register.......................................................282 EQ4_COEF2_HI Register........................................................282 EQ4_COEF2_LO Register.......................................................282 EQ4_COEF3_HI Register........................................................283 EQ4_COEF3_LO Register.......................................................283 EQ4_COEF4_HI Register........................................................283 EQ4_COEF4_LO Register.......................................................284 EQ5_COEF0_HI Register........................................................284 EQ5_COEF0_LO Register.......................................................284 EQ5_COEF1_HI Register........................................................285 EQ5_COEF1_LO Register.......................................................285 EQ5_COEF2_HI Register........................................................285 EQ5_COEF2_LO Register.......................................................286 EQ5_COEF3_HI Register........................................................286 EQ5_COEF3_LO Register.......................................................286 EQ5_COEF4_HI Register........................................................287 EQ5_COEF4_LO Register.......................................................287 EQ6_COEF0_HI Register........................................................287 EQ6_COEF0_LO Register.......................................................288 EQ6_COEF1_HI Register........................................................288 EQ6_COEF1_LO Register.......................................................288 EQ6_COEF2_HI Register........................................................289 EQ6_COEF2_LO Register.......................................................289 EQ7_COEF0_HI Register........................................................289 EQ7_COEF0_LO Register.......................................................290 EQ7_COEF1_HI Register........................................................290 EQ7_COEF1_LO Register.......................................................290 EQ7_COEF2_HI Register........................................................291 Rev. 0 \| Page 5 of 296 5 Page Parameter Test Conditions/Comments Min Typ ANALOG INPUT → ADC → DIGITAL OUTPUT ADC Resolution All ADCs 24 Dynamic Range −60 dBFS input at 1 kHz Unweighted (RMS) 93 A-weighted (RMS) 96 Signal-to-Noise Ratio A-weighted (rms), referred to full-scale output 96 THD + N −1 dBFS input at 1 kHz 0.01 Offset Error ±1 Gain Drift 100 Interchannel Isolation 85 PSRR AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 All other supplies (HPVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 DIGITAL MICROPHONE INPUT → ADC→ DIGITAL OUTPUT Dynamic Range −60 dBFS input at 1 kHz Unweighted (rms) 93 A-weighted (rms) 96 Signal-to-Noise Ratio A-weighted (rms) 96 THD + N −1 dBFS at 1 kHz 0.01 Offset Error ±1 Gain Drift 100 Interchannel Isolation 85 PSRR AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 All other supplies (HPVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 ANALOG INPUT → LINE OUTPUT Dynamic Range −60 dBFS input at 1 kHz Unweighted (RMS) 91 A-weighted (RMS) 94 Signal-to-Noise Ratio Differential line output, A-weighted (rms), referred to full-scale output 94 THD + N VOUT = 1 V, 1 kHz, RL=10 kΩ 0.013 VOUT = 0.5 V, 1 kHz, RL=10 kΩ 0.017 Interchannel Isolation 85 PSRR AVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 All other supplies (HPVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 ANALOG INPUT → HEADPHONE OUTPUT Dynamic Range −60 dBFS input at 1 kHz Unweighted (rms) 96 A-weighted (rms) 99 Signal-to-Noise Ratio A-weighted (rms), referred to full-scale output 99 THD + N POUT = 27 mW, 1 kHz, RL = 16 Ω 0.01 Interchannel Isolation 85 PSRR HPVDD ripple = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 All other supplies (AVDD, SPKVDD, DVDD, IOVDDx) = 100 mV p-p at 217 Hz, input referred for PGA gain = 0 dB 85 ADAU1373 Max Unit Bits dB dB dB % mV ppm/°C dB dB dB dB dB dB % mV ppm/°C dB dB dB dB dB dB % % dB dB dB dB dB dB % dB dB dB Rev. 0 \| Page 11 of 296 11 Page

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