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PDF ADAU1372 Data sheet ( Hoja de datos )
| Número de pieza | ADAU1372 | |
| Descripción | Low Power Codec | |
| Fabricantes | Analog Devices | |
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Data Sheet
Quad ADC, Dual DAC, Low Latency,
Low Power Codec
ADAU1372
FEATURES
APPLICATIONS
Low latency, 24-bit ADCs and DACs
102 dB SNR (through PGA and ADC with A-weighted filter)
107 dB dynamic range (through DAC and headphone with
A-weighted filter)
Serial port sample rates from 8 kHz to 192 kHz
4 single-ended analog inputs, configurable as microphone or
line inputs
Dual stereo digital microphone inputs
Stereo analog audio output, single-ended or differential,
configurable as either line output or headphone driver
PLL supporting any input clock rate from 8 MHz to 27 MHz
Full-duplex, asynchronous sample rate converters (ASRCs)
Power supplies
Analog and digital input/output of 1.8 V to 3.3 V
Low power (15.5 mW)
I2C and SPI control interfaces for flexibility
5 multipurpose pins supporting dual stereo digital
microphone inputs, mute, push-button volume controls
Handsets, headsets, and headphones
Bluetooth® handsets, headsets, and headphones
Personal navigation devices
Digital still and video cameras
GENERAL DESCRIPTION
The ADAU1372 is a codec with four inputs and two outputs, which
incorporates asynchronous sample rate converters. Optimized
for low latency and low power, the ADAU1372 is ideal for headsets,
handsets, and headphones. The ADAU1372 has built-in program-
mable gain amplifiers (PGAs); thus, with the addition of just a
few passive components and a crystal, the ADAU1372 provides
a solution for headset audio needs, microphone preamplifiers,
ADCs, DACs, headphone amplifiers, and serial ports for
connections to an external DSP.
Note that throughout this data sheet, multifunction pins, such as
SCL/SCLK, are referred to either by the entire pin name or by a
single function of the pin, for example, SCLK, when only that
function is relevant.
FUNCTIONAL BLOCK DIAGRAM
MICBIAS0
MICBIAS1
AIN0REF
AIN0
AIN1REF
AIN1
DMIC0_1/MP4
DMIC2_3/MP5
AIN2REF
AIN2
AIN3REF
AIN3
CM
MICROPHONE
BIAS GENERATORS
PGA
Σ-Δ ADC
PGA
Σ-Δ ADC
DIGITAL
MICROPHONE
INPUTS
PGA
Σ-Δ ADC
PGA
Σ-Δ ADC
ADAU1372
POWER
MANAGEMENT
LDO
REGULATOR
PLL
CLOCK
OSCILLATOR
DECIMATOR
DECIMATOR
INPUT/OUTPUT
SIGNAL ROUTING
Σ-Δ
DACs
DECIMATOR
DECIMATOR
BIDIRECTIONAL
ASRCS
SERIAL I/O PORT
Σ-Δ
DACs
I2C/SPI CONTROL
INTERFACE
ADC_SDATA1/CLKOUT/MP6
XTALI/MCLKIN
XTALO
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
Figure 1.
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADAU1372
Data Sheet
SPECIFICATIONS
Master clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits,
ambient temperature = 25°C, outputs line loaded with 10 kΩ.
ANALOG PERFORMANCE SPECIFICATIONS
Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted, PLL disabled, direct master clock.
Table 1.
Parameter
Test Conditions/Comments
Min Typ
Max
ANALOG-TO-DIGITAL CONVERTERS (ADCs)
ADC Resolution
All ADCs
24
Digital Attenuation Step
0.375
Digital Attenuation Range
95
INPUT RESISTANCE
Gain settings do not include 10 dB gain from
PGA_x_BOOST settings; this additional gain does not
affect input impedance; PGA_POP_DISx = 1
Single-Ended Line Input
0 dB gain
14.3
PGA Inputs
−12 dB gain
32.0
0 dB gain
20
+35.25 dB gain
0.68
SINGLE-ENDED LINE INPUT
PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1
Full-Scale Input Voltage
Scales linearly with AVDD
AVDD/3.63
AVDD = 1.8 V
0.49
AVDD = 1.8 V
1.38
AVDD = 3.3 V
0.90
AVDD = 3.3 V
2.54
Dynamic Range1
20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS)
AVDD = 1.8 V
97
AVDD = 3.3 V
102
With Flat 20 Hz to 20 kHz Filter
AVDD = 1.8 V
94
AVDD = 3.3 V
99
Signal-to-Noise Ratio (SNR)2
With A-Weighted Filter (RMS)
AVDD = 1.8 V
98
AVDD = 3.3 V
103
With Flat 20 Hz to 20 kHz Filter
AVDD = 1.8 V
96
AVDD = 3.3 V
100
Interchannel Gain Mismatch
40
Total Harmonic Distortion + Noise (THD + N) 20 Hz to 20 kHz, −1 dBFS input
AVDD = 1.8 V
−90
AVDD = 3.3 V
−94
Offset Error
±0.1
Gain Error
±0.2
Interchannel Isolation
CM capacitor = 22 µF
100
Power Supply Rejection Ratio (PSRR)
CM capacitor = 22 µF, 100 mV p-p at 1 kHz
55
SINGLE-ENDED PGA INPUT
PGA_ENx = 1, PGA_x_BOOST = 0
Full-Scale Input Voltage
Scales linearly with AVDD
AVDD/3.63
AVDD = 1.8 V
0.49
AVDD = 1.8 V
1.38
AVDD = 3.3 V
0.90
AVDD = 3.3 V
2.54
Dynamic Range1
20 Hz to 20 kHz, −60 dB input
With A-Weighted Filter (RMS)
AVDD = 1.8 V
96
AVDD = 3.3 V
102
With Flat 20 Hz to 20 kHz Filter
AVDD = 1.8 V
94
AVDD = 3.3 V
99
Unit
Bits
dB
dB
kΩ
kΩ
kΩ
kΩ
V rms
V rms
V p-p
V rms
V p-p
dB
dB
dB
dB
dB
dB
dB
dB
mdB
dB
dB
mV
dB
dB
dB
V rms
V rms
V p-p
V rms
V p-p
dB
dB
dB
dB
Rev. 0 | Page 4 of 92
5 Page 
ADAU1372
Data Sheet
DIGITAL TIMING SPECIFICATIONS
−40°C < TA < +85°C, IOVDD = 1.71 V to 3.63 V, DVDD = 1.045 V to 1.98 V.
Table 7. Digital Timing
Parameter
MASTER CLOCK
tMP
tMCLK
SERIAL PORT
tBL
tBH
tLS
tLH
tSS
tSH
tTS
tSOD
tSOTD
tMIN
37
77
40
40
10
10
5
5
0
tSOTX
SPI PORT
fSCLK
tCCPL
tCCPH
tCLS
tCLH
tCLPH
tCDS
tCDH
tCOD
I2C PORT
fSCL
tSCLH
tSCLL
tSCS
tSCR
tSCH
tDS
tSCF
tSDF
tBFT
MULTIPURPOSE AND POWER-
DOWN PINS
tGIL
tRLPW
DIGITAL MICROPHONE
tCF
tCR
tDS
tDE
80
80
5
100
80
10
10
0.6
1.3
0.6
0.6
100
0.6
20
40
tMAX Unit Description
125 ns MCLKIN period; 8 MHz to 27 MHz input clock using PLL
82 ns Internal MCLK period; direct MCLK and PLL output divided by 2
ns BCLK low pulse width (master and slave modes)
ns BCLK high pulse width (master and slave modes)
ns LRCLK setup; time to BCLK rising (slave mode)
ns LRCLK hold; time from BCLK rising (slave mode)
ns DAC_SDATA setup; time to BCLK rising (master and slave modes)
ns DAC_SDATA hold; time from BCLK rising (master and slave modes)
10 ns BCLK falling to LRCLK timing skew (master mode)
34 ns ADC_SDATAx delay; time from BCLK falling (master and slave modes)
30 ns BCLK falling to ADC_SDATAx driven in time-division multiplexing (TDM)
tristate mode
30 ns BCLK falling to ADC_SDATAx tristate in TDM tristate mode
6.25 MHz SCLK frequency
ns SCLK pulse width low
ns SCLK pulse width high
ns SS setup; time to SCLK rising
ns SS hold; time from SCLK rising
ns SS pulse width high
ns MOSI setup; time to SCLK rising
ns MOSI hold; time from SCLK rising
101 ns MISO delay; time from SCLK falling
400 kHz SCL frequency
µs SCL high
µs SCL low
µs SCL rise setup time (to SDA falling), relevant for repeated start condition
250 ns SCL and SDA rise time, CLOAD = 400 pF
µs SCL fall hold time (from SDA falling), relevant for start condition
ns SDA setup time (to SCL rising)
250 ns SCL fall time; CLOAD = 400 pF
250 ns SDA fall time; CLOAD = 400 pF; not shown in Figure 5
µs SCL rise setup time (to SDA rising), relevant for stop condition
1.5 × 1/fS
µs
ns
20 ns
20 ns
0 ns
MPx input latency; time until high or low value is read
PD low pulse width
Digital microphone clock fall time
Digital microphone clock rise time
Digital microphone valid data start time
Digital microphone valid data end time
Rev. 0 | Page 10 of 92
11 Page | ||
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