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PDF CY24272 Data sheet ( Hoja de datos )
| Número de pieza | CY24272 | |
| Descripción | Rambus XDR Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY24272
Rambus XDR™ Clock Generator with
Zero SDA Hold Time
Rambus‚ XDR™ Clock Generator with Zero SDA Hold Time
Features
■ Meets Rambus Extended Data Rate (XDR™) clocking
requirements
■ 25 ps typical cycle-to-cycle jitter
❐ –135 dBc/Hz typical phase noise at 20 MHz offset
■ 100 or 133 MHz differential clock input
■ 300–667 MHz high speed clock support
■ Quad (open drain) differential output drivers
■ Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
■ Spread Aware™
■ 2.5 V operation
■ 28-pin TSSOP package
Table 1. Device Comparison
CY24271
SDA hold time = 300 ns
(SMBus compliant)
RRC = 200 typical
(Rambus standard drive)
CY24272
SDA hold time = 0 ns
(I2C compliant)
RRC = 295 minimum
(Reduced output drive)
Logic Block Diagram
/BYPASS
EN
Bypass
MUX
REFCLK,REFCLKB
PLL
EN
RegA
EN
RegB
EN
RegC
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
EN
RegD
CLK3
CLK3B
SCL
SDA
ID0
ID1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42414 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 17, 2011
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CY24272
Table 5. Modes of Operation for CY24272
EN /BYPASS RegTest RegA RegB
LX
X XX
HX
1 XX
HL
0 XX
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
HH
0 00
0 00
0 00
0 00
0 01
0 01
0 01
0 01
0 10
0 10
0 10
0 10
0 11
0 11
0 11
0[4] 1[4] 1[4]
RegC
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1[4]
RegD
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1[4]
CLK0/CLK0B
High Z
REFCLK/
REFCLKB[3]
High Z
High Z
High Z
High Z
High Z
High Z
High Z
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B
High Z
High Z
High Z
Reserved for Vendor Test
REFCLK/
REFCLKB
REFCLK/
REFCLKB
REFCLK/
REFCLKB
High Z
High Z
High Z
High Z
High Z
CLK/CLKB
High Z
CLK/CLKB
High Z
High Z
CLK/CLKB CLK/CLKB
CLK/CLKB
High Z
High Z
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB CLK/CLKB
High Z
CLK/CLKB CLK/CLKB CLK/CLKB
High Z
High Z
High Z
High Z
High Z
CLK/CLKB
High Z
CLK/CLKB
High Z
High Z
CLK/CLKB CLK/CLKB
CLK/CLKB
High Z
High Z
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB CLK/CLKB
High Z
CLK/CLKB CLK/CLKB CLK/CLKB
Device ID and SMBus Device Address
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address designates a
write or read operation. Table 4 on page 4 shows the addresses
for four CY24272 devices on the same SMBus.
SMBus Protocol
The CY24272 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
DC specifications are modified to Rambus standard to support
1.8, 2.5, and 3.3 volt devices. Time out detection and packet
error protocol SMBus features are not supported.
Hold time for SDA is reduced relative to the CY24271, so that it
is compatible with I2C.
SMBus Data Byte Definitions
Three data bytes are defined for the CY24272. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
The definition of Byte 2 is shown in Table 6 on page 6,
Table 7 on page 6, and Table 8 on page 6. The upper five bits are
the revision numbers of the device and the lower three bits are
the ID numbers assigned to the vendor by Rambus.
Notes
3. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
4. Default mode of operation is at power up.
Document Number: 001-42414 Rev. *A
Page 5 of 16
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5 Page 
Test and Measurement Setup
Swing Current
Control
ISET
RRC
Figure 3. Clock Outputs
VTS
Measurement
Point
VT
CLK
R1
R2 R3 CS
ZCH
RT1
RT2
Differential Driver
CLKB
VTS
R1
R2 R3 CS
Measurement
Point
VT
ZCH
RT1
RT2
CY24272
Example External Resistor Values
and Termination Voltages for a 50 Channel
Parameter
Value
Unit
R1
R2
R3
RT1
RT2
CS
RRC
VTS
VT
33.0
18.0
17.0
60.4
301
2700
432
2.5
1.2
pF
V
V
Signal Waveforms
A physical signal that appears at the pins of a device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. Input and output voltage waveforms are defined as
shown in Figure 4 on page 12. Both rise and fall times are defined
between the 20% and 80% points of the voltage swing, with the
swing defined as VH–VL.
Figure 5 on page 12 shows the definition of the output crossing
point. The nominal crossing point between the complementary
outputs is defined as the 50% point of the DC voltage levels.
There are two crossing points defined: Vx+ at the rising edge of
CLK and Vx– at the falling edge of CLK. For some waveforms,
both Vx+ and Vx– are below Vx,nom (for example, if tCR is larger
than tCF).
Jitter
This section defines the specifications that relate to timing
uncertainty (or jitter) of the input and output waveforms. Figure 6
on page 12 shows the definition of cycle-to-cycle jitter with
respect to the falling edge of the CLK signal. Cycle-to-cycle jitter
is the difference between cycle times of adjacent cycles. Equal
requirements apply rising edges of the CLK signal. Figure 7 on
page 12 shows the definition of cycle-to-cycle duty cycle error
(tDC,ERR). Cycle-to-cycle duty cycle is defined as the difference
between tPW+ (high times) of adjacent differential clock cycles.
Equal requirements apply to tPW-, low times of the differential
click cycles.
Document Number: 001-42414 Rev. *A
Page 11 of 16
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| PDF Descargar | [ Datasheet CY24272.PDF ] | |
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