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PDF CY24271 Data sheet ( Hoja de datos )
| Número de pieza | CY24271 | |
| Descripción | Clock Generator | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CY24271 (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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CY24271
Rambus® XDR™ Clock Generator
Rambus® XDR™ Clock Generator
Features
■ Meets Rambus Extended Data Rate (XDR™) clocking
requirements
■ 25 ps typical cycle-to-cycle jitter
❐ 135 dBc/Hz typical phase noise at 20 MHz offset
■ 100 or 133 MHz differential clock input
■ 300–800 MHz high speed clock support
■ Quad (open drain) differential output drivers
■ Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4
■ Spread Aware™
■ 2.5 V operation
■ 28-pin TSSOP package
Functional Description
For a complete list of related documentation, click here.
Logic Block Diagram
/B YPA SS
EN
Bypass
MUX
REFCLK,REFC LKB
PLL
EN
RegA
EN
RegB
EN
RegC
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
EN
RegD
CLK3
CLK3B
SCL
SDA ID0 ID1
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-00411 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 20, 2016
1 page  
CY24271
Modes of Operation
The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.
Table 3 shows selection from one to all four of the outputs, the
Outputs Disabled Mode (EN = low), and Bypass Mode
(EN = high, /BYPASS = low). There is an option reserved for
vendor test. Disabled outputs are set to High Z.
At power up, the SMBus registers default to the last entry in
Table 3. The value at RegTest is 0. The values at RegA, RegB,
RegC, and RegD are all ‘1’. Thus, all outputs are controlled by
the logic applied to EN and /or BYPASS.
Table 3. Modes of Operation for CY24271
EN /BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B CLK1/CLK1B CLK2/CLK2B CLK3/CLK3B
LX
X X X X X High Z
High Z
High Z
High Z
HX
1 XXXX
Reserved for Vendor Test
HL
0
X X X X REFCLK/
REFCLK/
REFCLK/
REFCLK/
REFCLKB[4] REFCLKB
REFCLKB
REFCLKB
HH
0 0 0 0 0 High Z
High Z
High Z
High Z
HH
0 0 0 0 1 High Z
High Z
High Z
CLK/CLKB
HH
0 0 0 1 0 High Z
High Z
CLK/CLKB
High Z
HH
0 0 0 1 1 High Z
High Z
CLK/CLKB CLK/CLKB
HH
0
0100
High Z
CLK/CLKB
High Z
High Z
HH
0
0101
High Z
CLK/CLKB
High Z
CLK/CLKB
HH
0
0110
High Z
CLK/CLKB CLK/CLKB
High Z
HH
0
0111
High Z
CLK/CLKB CLK/CLKB CLK/CLKB
HH
0
1 0 0 0 CLK/CLKB
High Z
High Z
High Z
HH
0
1 0 0 1 CLK/CLKB
High Z
High Z
CLK/CLKB
HH
0
1 0 1 0 CLK/CLKB
High Z
CLK/CLKB
High Z
HH
0
1 0 1 1 CLK/CLKB
High Z
CLK/CLKB CLK/CLKB
HH
0
1 1 0 0 CLK/CLKB CLK/CLKB
High Z
High Z
HH
0
1 1 0 1 CLK/CLKB CLK/CLKB
High Z
CLK/CLKB
HH
HH
0
1 1 1 0 CLK/CLKB CLK/CLKB CLK/CLKB
High Z
0[5]
1[5] 1[5] 1[5] 1[5]
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
Notes
4. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
5. Default mode of operation is at power up.
Document Number: 001-00411 Rev. *F
Page 5 of 19
5 Page 
CY24271
AC Electrical Specifications
The AC Electrical specifications follow.
Parameter [24]
Description
tCYCLE
tJIT(cc)
Clock Cycle time[25]
Jitter over 1-6 clock cycles at 400–635 MHz[26]
Jitter over 1-6 clock cycles at 638–800 MHz
L20 Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz
(In addition, device must not exceed
L(f) = 10log[1+(50x106/f)2.4] –138 for f = 1 MHz to 100 MHz
except for the region near f = REFCLK/Q where Q is the value of the
internal reference divider.)
533 MHz and faster output
tJIT(hper,cc)
Cycle-to-cycle duty cycle error at 400–635 MHz
Cycle-to-cycle duty cycle error at 636–800 MHz
tSKEW
Drift in tSKEW when ambient temperature
70 °C and supply voltage varies between
varies
2.375
between 0 °C and
V and 2.625 V.[27]
DC Long term average output duty cycle
tEER,SCC
tCR,tCF
PLL output phase error when tracking SSC
Output rise and fall times at 400–800 MHz (measured at 20%–80%
of output voltage)
tCR,CF
Difference between output rise and fall times on the same pin of the
single device (20%–80%) of 400–800 MHz[28]
Min
1.25
–
–
–
–
–
–
–
45%
–100
120
–
Typ
–
25
25
–135
–
25
25
–
50
–
–
–
Max
3.34
40
30
–128
Unit
ns
ps
ps
dBC/Hz
TBD
40
30
15
55%
100
300
100
ps
ps
ps
tCYCLE
ps
ps
ps
Notes
24. Not 100% tested except VIXCLK and VIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
25. Max and min output clock cycle times are based on nominal outputs frequency of 300 and 800 MHz, respectively. For spread spectrum modulated differential or
single-ended REFCLK, the output clock tracks the modulation of the input.
26. Output short term jitter spec is the absolute value of the worst case deviation.
27. toSpKeErWatiinsgthteemtimpeinragtudrieffearnedncseupbpeltywveoelntaagneycthwaongoef .the four differential clocks and is measured at common mode voltage. tSKEW is the change in tSKEW when the
28. tCR,CF applies only when appropriate RRC and output resistor network resistor values are selected to match pull up and pull down currents.
Document Number: 001-00411 Rev. *F
Page 11 of 19
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet CY24271.PDF ] | |
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