PDF CY8C22345 Data sheet ( Hoja de datos )

Número de pieza	CY8C22345
Descripción	Automotive PSoC Programmable System-on-Chip
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY8C21345, CY8C22345, CY8C22545 PSoC® Programmable System-on-Chip™ Features ■ Powerful Harvard Architecture Processor: ❐ M8C Processor Speeds up to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0V to 5.25V Operating Voltage ❐ Industrial Temperature Range: -40°C to +85°C ■ Advanced Peripherals (PSoC Blocks) ❐ Six Analog Type “E” PSoC Blocks provide: • Single or Dual 8-Bit ADC • Comparators (up to Four) ❐ Up to Eight Digital PSoC Blocks provide: • 8 to 32-Bit Timers, Counters, and PWMs • One Shot, Multi Shot Mode Support in Timers and PWMs • PWM with Deadband Support in One Digital Block • Shift Register, CRC, and PRS Modules • Full Duplex UART • Multiple SPI™ Masters or Slaves, Variable Data Length Support: 8, 9, ...,16-bit • Can be Connected to all GPIO Pins ❐ Complex Peripherals by Combining Blocks ❐ Shift Function Support for FSK Detection ❐ Powerful Synchronize Feature Support. Analog Module Operations can be Synchronized by Digital Blocks or External Signals. ■ High Speed 10-Bit SAR ADC with Sample and Hold Optimized for Embedded Control ■ Precision, Programmable Clocking: ❐ Internal ± 5% 24/48 MHz Oscillator across the Industrial Temperature Range High Accuracy❐www.DataSheet4U.net 24 MHz with Optional 32 kHz Crystal and PLL ❐ Optional External Oscillator, up to 24 MHz ❐ Internal/External Oscillator for Watchdog and Sleep ■ Flexible On-Chip Memory: ❐ Up to 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles ❐ Up to 1K Byte SRAM Data Storage ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash ■ Optimized CapSense Resource: ❐ Two IDAC Support up to 640 µA Source Current to Replace External Resistor ❐ Two Dedicated Clock Resources for CapSense: • CSD_CLK: 1/2/4/8/16/32/128/256 Derive from SYSCLK • CNT_CLK: 1/2/4/8 Derive from CSD_CLK ❐ Dedicated 16-Bit Timers/Counters for CapSense Scanning ❐ Support Dual CSD Channels Simultaneous Scanning ■ Programmable Pin Configurations: ❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 38 Analog Inputs on GPIO ❐ Configurable Interrupt on all GPIO ■ Additional System Resources: ❐ I2C™ Slave, Master, and MultiMaster to 400 kHz, Supports Hardware Addressing Feature ❐ Watchdog and Sleep Timers ❐ User Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference ❐ Supports RTC Block into Digital Peripheral Logic Top Level Block Diagram PSoC Core Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers Global Digital Interconnect Global Analog Interconnect SRAM 1K Interrupt Controller SROM Flash 16K CPU Core (M8C) Sleep and Watchdog Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array DBC DBC DCC DCC ROW 1 DBC DBC DCC DCC ROW 2 CapSense Digital Resource ANALOG SYSTEM Analog Input Muxing(L,R) Analog Ref = Analog Block Array CTE CTE CTE CTE SCE SCE 10-bit SAR ADC Digital Clocks MACs I2C POR and LVD System Resets SYSTEM RESOURCES Internal Voltage Ref. Cypress Semiconductor Corporation • 198 Champion Court Document Number: 001-43084 Rev. H • San Jose, CA 95134-1709 • 408-943-2600 Revised March 16, 2009 [+] Feedback 1 page CY8C21345, CY8C22345, CY8C22545 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is www.DataSheet4U.net available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. Document Number: 001-43084 Rev. H Page 5 of 27 [+] Feedback 5 Page CY8C21345, CY8C22345, CY8C22545 Table 6. Register Map Bank 0 Table: User Space (continued) DCC13DR1 3D W DCC13DR2 3E RW DCC13CR0 3F # Shaded fields are Reserved and must not be accessed. 7D RW 7E RW 7F RW Table 7. Register Map Bank 1 Table: Configuration Space RDI1RO0 BD RW DAC0_D RDI1RO1 BE RW CPU_SCR1 RDI1DSM BF RW CPU_SCR0 # Access is bit specific. * has a different meaning. FD RW FE # FF # PRT0DM0 0 RW PRT0DM1 1 RW PRT0IC0 2 RW PRT0IC1 3 RW PRT1DM0 4 RW PRT1DM1 5 RW PRT1IC0 6 RW PRT1IC1 7 RW PRT2DM0 8 RW PRT2DM1 9 RW PRT2IC0 0A RW PRT2IC1 0B RW PRT3DM0 0C RW PRT3DM1 0D RW PRT3IC0 0E RW PRT3IC1 0F RW PRT4DM0 10 RW CMP0CR1 PRT4DM1 11 RW CMP0CR2 PRT4IC0 12 RW PRT4IC1 13 RW VDAC50CR0 14 RW CMP1CR1 15 RW CMP1CR2 16 RW 17 RW VDAC51CR0 18 RW CSCMPCR0 19 RW CSCMPGOEN 1A RW CSLUTCR0 1B RW CMPCOLMUX www.DataSheet4U.net 1C RW CMPPWMCR 1D RW CMPFLTCR 1E RW CMPCLK1 1F RW CMPCLK0 DBC00FN 20 RW CLK_CR0 DBC00IN 21 RW CLK_CR1 DBC00OU 22 RW ABF_CR0 DBC00CR1 23 RW AMD_CR0 DBC01FN 24 RW CMP_GO_EN DBC01IN 25 RW CMP_GO_EN1 DBC01OU 26 RW AMD_CR1 DBC01CR1 27 RW ALT_CR0 DCC02FN 28 RW ALT_CR1 DCC02IN 29 RW CLK_CR2 DCC02OU 2A RW DBC02CR1 2B RW CLK_CR3 DCC03FN 2C RW TMP_DR0 DCC03IN 2D RW TMP_DR1 DCC03OU 2E RW TMP_DR2 DBC03CR1 2F RW TMP_DR3 DBC10FN 30 RW DBC10IN 31 RW DBC10OU 32 RW ACB00CR1* DBC10CR1 33 RW ACB00CR2* Shaded fields are Reserved and must not be accessed. Document Number: 001-43084 Rev. H 40 RW ASC10CR0 80* RW 41 RW 81 RW 42 RW 82 RW 43 83 RW 44 RW ASD11CR0* 84* RW 45 RW 85 RW 46 RW 86 RW 47 87 RW 48 RW 88 RW 49 RW 89 RW 4A RW 8A RW 4B 8B RW 4C RW 8C RW 4D RW 8D RW 4E RW 8E RW 4F 8F RW 50 RW 90 RW GDI_O_IN 51 RW 91 RW GDI_E_IN 52 RW 92 RW GDI_O_OU 53 RW 93 RW GDI_E_OU 54 RW 94 RW 55 RW 95 RW 56 RW 96 RW 57 RW 97 RW 58 # 98 RW MUX_CR0 59 RW 99 RW MUX_CR1 5A RW 9A RW MUX_CR2 5B RW 9B RW MUX_CR3 5C RW 9C RW DAC_CR1# 5D RW 9D RW OSC_GO_EN 5E RW 9E RW OSC_CR4 5F RW 9F RW OSC_CR3 60 RW GDI_O_IN_CR A0 RW OSC_CR0 61 RW GDI_E_IN_CR A1 RW OSC_CR1 62 RW GDI_O_OU_CR A2 RW OSC_CR2 63 RW GDI_E_OU_CR A3 RW VLT_CR 64 RW RTC_H A4 RW VLT_CMP 65 RW RTC_M A5 RW ADC0_TR* 66 RW RTC_S A6 RW ADC1_TR* 67 RW RTC_CR A7 RW V2BG_TR 68 RW SADC_CR0 A8 RW IMO_TR 69 RW SADC_CR1 A9 RW ILO_TR 6A RW SADC_CR2 AA RW BDG_TR 6B RW SADC_CR3TRIM AB RW ECO_TR 6C RW SADC_CR4 AC RW MUX_CR4 6D RW I2C0_AD AD RW MUX_CR5 6E RW AE RW MUX_CR6 6F RW AF RW MUX_CR7 70 RW RDI0RI B0 RW CPU A 71 RW RDI0SYN B1 RW CPU_T1 72 RW RDI0IS B2 RW CPU_T2 73 RW RDI0LT0 B3 RW CPU_X # Access is bit specific. * has a different meaning. C0 RW C1 RW C2 RW C3 RW C4 RW C5 RW C6 RW C7 RW C8 # C9 RW CA RW CB RW CC # CD RW CE RW CF RW D0 RW D1 RW D2 RW D3 RW D4 RW D5 RW D6 RW D7 RW D8 RW D9 RW DA RW DB RW DC RW DD RW DE RW DF RW E0 RW E1 RW E2 RW E3 RW E4 R E5 RW E6 RW E7 RW E8 W E9 W EA RW EB W EC RW ED RW EE RW EF RW F0 # F1 # F2 # F3 # Page 11 of 27 [+] Feedback 11 Page

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