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PDF CY8C22345H Data sheet ( Hoja de datos )
| Número de pieza | CY8C22345H | |
| Descripción | Automotive Programmable System-on-Chip | |
| Fabricantes | Cypress Semiconductor | |
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Automotive PSoC®
Programmable System-on-Chip™
Features
■ Automotive Electronics Council (AEC) Q100 qualified
■ Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Automotive A-grade: 3.0 V to 5.25 V operation at –40 °C to
+85 °C temperature range
❐ Automotive E-grade: 4.75 V to 5.25 V operation at –40 °C to
+125 °C temperature range
■ Advanced peripherals (PSoC® blocks)
❐ Six analog Type ‘E’ PSoC blocks provide:
• Up to four comparators with digital-to-analog converters
(DAC) references
• Up to 10-bit single or dual analog-to-digital converters
(ADCs)
❐ Up to eight digital PSoC blocks provide:
• 8 to 32-bit timers, counters, and pulse width modulators
(PWMs)
• One-shot, multi-shot mode in timers and PWMs
• PWM with deadband in one digital block
• Shift register, cyclical redundancy check (CRC), and
pseudo random sequence (PRS) modules
• Full- or half-duplex UARTs
• SPI masters or slaves, 8- to 16-bit variable data length
• Connectable to all general-purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
❐ Powerful synchronization support, analog module operations
can be synchronized by digital blocks or external signals.
■ High-speed 10-bit successive approximation register (SAR)
ADC with sample and hold optimized for embedded control
■ CY8C22345H devices integrate Immersion® TouchSense®
haptics technology for ERM drive control
■ Precision, programmable clocking
❐ Internal oscillator up to 24 MHz
❐ High accuracy 24 MHz with optional 32-kHz crystal and
phase locked loop (PLL)
❐ Optional external oscillator, up to 24 MHz
❐ Internal low speed, low-power oscillator for watchdog and
sleep functionality
■ Flexible on-chip memory
❐ Up to 16 KB flash program storage, 1000 erase/write cycles
❐ Up to 1 KB SRAM data storage
❐ In-System Serial Programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Optimized CapSense® resource
❐ Supports two CapSense channels with simultaneous
scanning
❐ Two current DACs provide programmable sensor tuning in
firmware
❐ Two dedicated clock resources for CapSense
❐ Two dedicated 16-bit timers/counters for CapSense
scanning
■ Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
■ Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
❐ Analog input on all GPIOs
❐ Configurable interrupt on all GPIOs
■ Additional system resources:
❐ I2C master, slave, or multi-master
• Operation up to 400 kHz
• Hardware address detection feature
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
❐ Hardware real time clock (RTC) block
Block Diagram
PSoC CORE
Port 4 Port 3 Port 2 Port 1 Port 0
System Bus
Global Digital
Interconnect
SRAM
1KB/512B
Interrupt
Controller
Global Analog Interconnect
SROM Flash 16K/8K
CPU Core (M8C)
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital Block
Array
CapSense Digital
Resources
ANALOG SYSTEM
10-bit SAR
ADC
Analog
Block
Array
Analog
Ref
Analog
Input
Muxing
Digital
Clocks
Multiply
Accum.
I2C
RTC
POR and LVD
System Resets
SYSTEM RESOURCES
Internal
Voltage
Ref.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-55397 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 18, 2011
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Additional System Resources
System Resources, some of which are listed in the previous
sections, provide additional capability useful for complete
systems. Additional resources include a MAC, low voltage
detection, and power on reset. The merits of each system
resource are:
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■ Additional digital resources and clocks dedicated to and
optimized for CapSense.
■ RTC hardware block.
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■ The I2C module provides 0 to 400 kHz communication over two
wires. Slave, master, and multi-master modes are all
supported.
■ Low voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced power
on reset (POR) circuit eliminates the need for a system
supervisor.
■ An internal voltage reference provides an absolute reference
for the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have varying numbers of digital and analog
blocks. The following table lists the resources available for
specific PSoC device groups. The PSoC families covered by this
datasheet are highlighted in the table.
Table 1. PSoC Device Characteristics
PSoC Part
Number
CY8C29x66[2]
CY8C28xxx
CY8C27x43
CY8C24x94[2]
CY8C24x23A[2]
CY8C23x33
CY8C22x45[2]
CY8C21x45[2]
CY8C21x34[2]
CY8C21x23
CY8C20x34[2]
up to
64
up to
44
up to
44
up to
56
up to
24
up to
25
up to
38
up to
38
up to
28
up to
16
up to
28
4 16 up to 4
12
4 12 2 KB 32 KB
up to up to up to up to up to up to 1 KB 16 KB
3 12 44 4 6 16
2 8 up to 4 4 12 256 16 KB
12 Bytes
1 4 up to 2 2 6 1 KB 16 KB
48
1 4 up to 2 2 6 256 4 KB
12 Bytes
1 4 up to 2 2 4 256 8 KB
12 Bytes
2 8 up to 0 4 6[3] 1 KB 16 KB
38
1 4 up to 0 4 6[3] 512 8 KB
38 Bytes
1 4 up to 0 2 4[3] 512 8 KB
28 Bytes
1 4 up to 0 2 4[3] 256 4 KB
8 Bytes
0 0 up to 0 0 3[3, 4] 512 8 KB
28 Bytes
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense® block.
Document Number: 001-55397 Rev. *I
Page 5 of 36
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CY8C21345, CY8C21645
CY8C22345, CY8C22345H, CY8C22645
Registers
This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer to the PSoC
Technical Reference Manual for CY8C21x45 and CY8C22x45 devices.
Register Conventions
The register conventions specific to this section are listed in the
following table.
Table 4. Abbreviations
Convention
RW
R
W
L
C
#
Description
Read and write register or bit(s)
Read register or bit(s)
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
Register Mapping Tables
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks. The XIO bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XIO bit
is set the user is in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Document Number: 001-55397 Rev. *I
Page 11 of 36
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