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PDF MAX9268 Data sheet ( Hoja de datos )

Número de pieza MAX9268
Descripción Gigabit Multimedia Serial Link Deserializer
Fabricantes Maxim Integrated Products 
Logotipo Maxim Integrated Products Logotipo



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19-5211; Rev 2; 1/11
EVAALVUAAILTAIOBNLEKIT
Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
General Description
The MAX9268 deserializer utilizes Maxim’s gigabit
multimedia serial link (GMSL) technology. The MAX9268
deserializer features an LVDS system interface for reduced
pin count and a smaller package, and pairs with any GMSL
serializer to form a complete digital serial link for joint
transmission of high-speed video, audio, and bidirectional
control data.
The MAX9268 allows a maximum serial payload data
rate of 2.5Gbps for a 15m shielded twisted-pair (STP)
cable. The deserializer operates up to a maximum
output clock rate of 104MHz (3-channel LVDS) or 78MHz
(4-channel LVDS). This serial link supports display
panels from QVGA (320 x 240) to WXGA (1280 x 800) and
higher with 24-bit color.
The 3-channel mode outputs an LVDS clock, three lanes
of LVDS data (21 bits), UART control signals, and one I2S
audio channel consisting of three signals. The 4-channel
mode outputs an LVDS clock, four lanes of LVDS data
(28 bits), UART control signals, an I2S audio channel,
and auxiliary control outputs. The three audio outputs
form a standard I2S interface, supporting sample rates
from 8kHz to 192kHz and audio word lengths of 4 to 32
bits. The embedded control channel forms a full-duplex,
differential, 100kbps to 1Mbps UART link between the
serializer and deserializer. An electronic control unit (ECU),
or microcontroller (FC), can be located on the serializer
side of the link (typical for video display), on the MAX9268
side of the link (typical for image sensing), or on both sides.
In addition, the control channel enables ECU/FC control of
peripherals on the remote side, such as backlight control,
grayscalewww.DataSheet4U.net gamma correction, camera module, and touch
screen. Base-mode communication with peripherals uses
either I2C or the GMSL UART format. In addition, the
MAX9268 features a bypass mode that enables full-duplex
communication using custom UART formats.
The GMSL serializer driver preemphasis, along with the
MAX9268 channel equalizer, extends the link length and
enhances the link reliability. Spread spectrum is available
to reduce EMI on the LVDS and control outputs of the
MAX9268. The serial line inputs comply with ISO 10605 and
IEC 61000-4-2 ESD protection standards.
The core supply for the MAX9268 is 3.3V. The I/O supply
ranges from 1.8V to 3.3V. The MAX9268 is available in
a 48-pin TQFP package (7mm x 7mm) with an exposed
pad, and is specified over the -40NC to +105NC automotive
temperature range.
Features
S Pairs with Any GMSL Serializer
S 2.5Gbps Payload-Rate AC-Coupled Serial Link
S Scrambled 8b/10b Line Coding
S Supports WXGA (1280 x 800) with 24-Bit Color
S 8.33MHz to 104MHz (3-Channel LVDS) or 6.25MHz
to 78MHz (4-Channel LVDS) Output Clock
S 4-Bit to 32-Bit Word Length, 8kHz to 192kHz I2S
Audio Channel Supports High-Definition Audio
S Embedded Half-/Full-Duplex Bidirectional Control
Channel (100kbps to 1Mbps)
S Two 3-Level Inputs Support 9 Device Addresses
S Interrupt Supports Touch-Screen Functions for
Display Panels
S I2C Master for Peripherals
S Equalizer for Serial Link Input
S Programmable Spread Spectrum on the LVDS and
Control Outputs for Reduced EMI
S Serial-Data Clock Recovery Eliminates an External
Clock
S Automatic Data-Rate Detection Allows On-the-Fly
Data-Rate Change
S Built-In PRBS Generator for BER Testing of the
Serial Link
S ISO 10605 and IEC 61000-4-2 ESD Protection
S -40NC to +105NC Operating Temperature Range
S 1.8V to 3.3V I/O and 3.3V Core Supplies
S Patent Pending
Ordering Information
PART
TEMP RANGE PIN-PACKAGE
MAX9268GCM/V+ -40NC to +105NC 48 TQFP-EP*
MAX9268GCM/V+T -40NC to +105NC 48 TQFP-EP*
/V denotes an automotive qualified product.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
T = Tape and reel.
Applications
High-Resolution Automotive Navigation
Rear-Seat Infotainment
Megapixel Camera Systems
________________________________________________________________ Maxim Integrated Products   1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.

1 page




MAX9268 pdf
Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
AC ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.0V to 3.6V, VIOVDD = 1.7V to 3.6V, RL = 100Ω Q1% (differential), TA = -40NC to +105NC, unless otherwise noted.
Typical values are at VAVDD = VDVDD = VIOVDD = 3.3V, TA = +25NC.)
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
LVDS Output Pulse Position
tPPOSN
fTXCLKOUT_
=
12.5MHz
N/7 x tCLK
- 250
N/7 x
tCLK
N/7 x tCLK
+ 250
N = 0 to 6, tCLK =
1/fTXCLKOUT_,
fTXCLKOUT_ = 33MHz
fTXCLKOUT_ =
104MHz
(Figure 7)
fTXCLKOUT_ = 78MHz
N/7 x tCLK N/7 x N/7 x tCLK
- 200 tCLK + 200
N/7 x tCLK N/7 x N/7 x tCLK
- 125 tCLK + 125
fTXCLKOUT_ = 104MHz
N/7 x tCLK N/7 x N/7 x tCLK
- 100 tCLK + 100
ps
LVDS Output Enable Time
tLVEN
From the last bit of the enable UART
packet to VOS = 1125mV
100 Fs
LVDS Output Disable Time
Deserializer Delay
Reverse Control-Channel Output
Rise Time
tLVDS
tSD
tR
From the last bit of the enable UART
packet to VOS = 0V
Figure 8 (Note 4)
No forward-channel data transmission
(Figure 1)
180
100
3540
400
Fs
Bits
ns
Reverse Control-Channel Output
Fall Time
tF
No forward-channel data transmission
(Figure 1)
180
400 ns
Lock Time
Power-Up Time
I2S OUTPUT TIMING
WS Jitter
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SCK Jitter
Audio Skew Relative to Video
SCK, SD, WS Rise-and-Fall Time
tLOCK
tPU
tAJ-WS
tAJ-SCK
tASK
tR, tF
Figure 9
Figure 10
tWS = 1/fWS,
rising (falling)
edge to falling
(rising) edge
(Note 5)
fWS = 48kHz or 44.1kHz
fWS = 96kHz
fWS = 192kHz
nWS = 16 bits, fWS =
tSCK = 1/fSCK,
rising edge to
rising edge
48kHz or 44.1kHz
nWS = 24 bits, fWS =
96kHz
nWS = 32 bits,
fWS = 192kHz
Video and audio synchronized
20% to 80%
CL = 10pF, DCS = 1
CL = 5pF, DCS = 0
3.6 ms
4.1 ms
0.4e-3
x tWS
0.8e-3
x tWS
1.6e-3
x tWS
13e-3
x tSCK
39e-3
x tSCK
0.1
x tSCK
3 x tWS
0.5e-3
x tWS
1e-3
x tWS
2e-3
x tWS
16e-3
x tSCK
48e-3
x tSCK
0.13
x tSCK
4 x tWS
0.3 3.1
0.4 3.8
ns
ns
Fs
ns
SD, WS Valid Time Before SCK
tDVB
tSCK = 1/fSCK (Figure 11)
0.35 x
tSCK
0.5 x
tSCK
ns
SD, WS Valid Time After SCK
tDVA
tSCK = 1/fSCK (Figure 11)
0.35 x
tSCK
0.5 x
tSCK
ns
Note 2: Minimum IIN due to voltage drop across the internal pullup resistor.
Note 3: Measured in serial link bit times. Bit time = 1/(30 x fTXCLKOUT_) for BWS = GND. Bit time = 1/(40 x fTXCLKOUT_) for VBWS =
VIOVDD.
Note 4: Rising to rising-edge jitter can be twice as large.
_______________________________________________________________________________________   5

5 Page





MAX9268 arduino
Gigabit Multimedia Serial Link Deserializer
with LVDS System Interface
TXOUT_-
TXCLKOUT-
TXOUT_+
TXCLKOUT+
VOS(-)
TXOUT_+
TXCLKOUT+
RL/2
VOD
TXOUT_-,
TXCLKOUT-
RL/2
GND
((TXOUT_+) + (TXOUT_-))/2
((TXCLKOUT+) + (TXCLKOUT-))/2
VOS
VOS(+)
DVOS = |VOS(+) - VOS(-)|
VOS(-)
(TXOUT_+) - (TXOUT_-)
(TXCLKOUT+) - (TXCLKOUT-)
VOD(-)
Figure 3. LVDS Output Parameters
tR
TXCLKOUT+
TXCLKOUT-
TXOUT0+ TO TXOUT3+
TXOUT0- TO TXOUT3-
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Figure 4. Worst-Case Pattern Output
tR
TX/
SCL
CNTL_
tF
VOD(+)
DVOD = |VOD(+) - VOD(-)|
VOD = 0V
tF VOD(-)
tHOLD
tSET
RX/
SDA
PS
Figure 5. I2C Timing Parameters
SP
______________________________________________________________________________________   11

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