PDF CY23FS08 Data sheet ( Hoja de datos )

Número de pieza	CY23FS08
Descripción	Failsafe 2.5 V/3.3 V Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY23FS08 Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Features ■ Internal DCXO for continuous glitch-free operation ■ Zero input-output propagation delay ■ 100 ps typical output cycle-to-cycle jitter ■ 110 ps typical output-output skew ■ 1 MHz to 200 MHz reference input ■ Supports industry standard input crystals ■ 200 MHz (commercial), 166 MHz (industrial) outputs ■ 5 V-tolerant inputs ■ Phase-locked loop (PLL) bypass mode ■ Dual reference inputs ■ 28-pin SSOP ■ Split 2.5 V or 3.3 V output power supplies ■ 3.3 V core power supply ■ Industrial temperature available Logic Block Diagram REFSEL REF1 REF2 FBK XIN XOUT DCXO FailsafeTM Block www.DataSheet4U.com S[4:1] Decoder 4 Functional Description The CY23FS08 is a FailSafe™ Zero Delay Buffer with two reference clock inputs and eight phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. Continuous, glitch-free operation is achieved by using a DCXO, which serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS08 is that the DCXO is in fact the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal connected to the DCXO, must be chosen to be an integer factor of the frequency of the reference clock. This factor is set by four select lines: S[4:1]. see Table 2. The CY23FS08 has three split power supplies; one for core, another for Bank A outputs, and the third for Bank B outputs. Each output power supply, except VDDC can be connected to either 2.5 V or 3.3 V. VDDC is the power supply pin for internal circuits and must be connected to 3.3 V. 4 CLKA[1:4] PLL 4 CLKB[1:4] FAIL# /SAFE Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-07518 Rev. F • San Jose, CA 95134-1709 • 408-943-2600 Revised January 7, 2011 [+] Feedback 1 page Figure 3. Fail#/Safe Timing Formula CY23FS08 Table 3. Failsafe Timing Table Parameter Description tFSL Fail#/Safe Assert Delay tFSH Fail#/Safe Deassert Delay Conditions Measured at 80% to 20%, Load = 15 pF Measured at 80% to 20%, Load = 15 pF Min Max See Figure 3 See Figure 3 Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range Unit ns ns Reference Reference + 300 ppm Reference - 300 ppm Reference Off Output Fail#/Safe tFSL Output + 300 ppm Output - 300 ppm tFSH Time www.DataSheet4U.com Document Number: 38-07518 Rev. F Page 5 of 15 [+] Feedback 5 Page CY23FS08 DC Electrical Characteristics Parameter VIL VIH IIL IIH IOL Description Input Low Voltage Input High Voltage Input Low Current Input High Current Output Low Current IOH Output High Current IDDQ Quiescent Current Test Conditions Min Typ Max Unit CMOS Levels, 30% of VDD CMOS Levels, 70% of VDD VIN = VSS (100k pull up only) VIN = VDD (100k pull down only) VOL = 0.5 V, VDD = 2.5 V VOL = 0.5 V, VDD = 3.3 V VOH = VDD – 0.5 V, VDD = 2.5 V VOH = VDD – 0.5 V, VDD = 3.3 V All Inputs grounded, PLL and DCXO in bypass mode, Reference Input = 0 – 0.7×VDD – – – – – – – – 0.3×VDD V – –V – 50 µA – 50 µA 18 – mA 20 – mA 18 – mA 20 – mA – 250 µA Switching Characteristics Parameter[7] Description fREF Reference Frequency fOUT Output Frequency fXIN tDC tSR(I) tSR(O) DCXO Frequency Duty Cycle Input Slew Rate Output Slew Rate tSK(O) tSK(IB) tSK(PP) t()[6] tD()[6] tJ(CC) Output to Output Skew Intrabank Skew Part to Part Skew Static Phase Offset Dynamic Phase Offset Cycle-to-Cycle Jitter tLOCK Lock Time Ordering Information Part Number Pb-free CY23FS08OXI CY23FS08OXIT wwwC.YD2a3taFSSh0e8eOt4XUC.com CY23FS08OXCT Test Conditions Commercial Grade Industrial Grade 15 pF Load, Commercial Grade 15 pF Load, Industrial Grade Measured at VDD/2 Measured on REF1 Input, 30% to 70% of VDD Measured from 20% to 80% of VDD = 3.3V, 15 pF Load Measured from 20% to 80% of VDD =2.5V, 15 pF Load All outputs equally loaded, measured at VDD/2 All outputs equally loaded, measured at VDD/2 Measured at VDD/2 Measured at VDD/2 Measured at VDD/2 Load = 15 pF, fOUT 6.25 MHz At room temperature with 18.432 MHz Crystal Min 1.04 1.04 1.70 1.70 8.0 47 0.5 0.8 0.4 – – – – – – – – Typ Max Unit – 200 MHz – 166.7 MHz – 200 MHz – 166.7 MHz – 30 MHz – 53 % – 4.0 V/ns – 4.0 V/ns – 3.0 V/ns 110 200 ps – 75 ps – 500 ps – 250 ps – 500 ps 100 200 ps 18 35 psRMS 70 – ms Package Type 28-pin SSOP 28-pin SSOP – Tape and Reel 28-pin SSOP 28-pin SSOP – Tape and Reel Product Flow Industrial, –40 °C to 85 °C Industrial, –40 °C to 85 °C Commercial, 0 °C to 70 °C Commercial, 0 °C to 70 °C Notes 6. 7. TPhaeratm(e)terersfegreunacraenfeteeeddbabcykdienspiugtndaenladycihsagraucatrearnizteaetidonfo, rnoatm10a0xi%mutemst4e:d1iinnppurot deudcgteiorna.tio between the two signals as long as tSR(I) is maintained. Document Number: 38-07518 Rev. *F Page 11 of 15 [+] Feedback 11 Page

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