PDF CY23FS04 Data sheet ( Hoja de datos )

Número de pieza	CY23FS04
Descripción	2.5 V/3.3 V Zero Delay Buffer
Fabricantes	Cypress Semiconductor
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No Preview Available ! CY23FS04 Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Failsafe™ 2.5 V/3.3 V Zero Delay Buffer Features ■ Internal digital controlled crystal oscillator (DCXO) for continuous glitch-free operation ■ Zero input-output propagation delay ■ Low jitter (35 ps max RMS) outputs ■ Low output-to-output skew (200 ps max) ■ 4.17 MHz to 166.7 MHz reference input ■ Supports industry standard input crystals ■ 166.7 MHz outputs ■ 5 V tolerant Inputs ■ Phase-locked loop (PLL) bypass mode ■ Dual reference inputs ■ 16-Pin thin shrunk small outline package (TSSOP) ■ 2.5 V or 3.3 V output power supplies ■ 3.3 V core power supply ■ Industrial temperature range Logic Block Diagram XIN XOUT REFSEL DCXO Functional Description The CY23FS04 is a FailSafe zero delay buffer with two reference clock inputs and four phase-aligned outputs. The device provides an optimum solution for applications where continuous operation is required in the event of a primary clock failure. The continuous, glitch-free operation is achieved by using a DCXO. This serves as a redundant clock source in the event of a reference clock failure by maintaining the last frequency and phase information of the reference clock. The unique feature of the CY23FS04 is that the DCXO is the primary clocking source, which is synchronized (phase-aligned) to the external reference clock. When this external clock is restored, the DCXO automatically resynchronizes to the external clock. The frequency of the crystal that is connected to the DCXO must be an integer factor of the frequency of the reference clock. This factor is set by two select lines: S[2:1], see Configuration Table on page 3. The output power supply VDD can be connected to either 2.5 V or 3.3 V. VDDC is the power supply pin for internal circuits and must be connected to 3.3 V. For a complete list of related documentation, click here. REF1 REF2 FBK FailsafeTM Block S[2:1] Decoder 2 PLL 2 CLKA[2:1] 2 CLKB[2:1] FAIL# /SAFE Cypress Semiconductor Corporation • 198 Champion Court Document Number: 38-07304 Rev. L • San Jose, CA 95134-1709 • 408-943-2600 Revised September 27, 2016 1 page CY23FS04 Figure 4. FailSafe Timing Diagram: Input Reference Slowly Drifting Out of FailSafe Capture Range Reference Reference + 300 ppm Reference - 300 ppm Reference Off Output Fail#/Safe Output + 300 ppm Output - 300 ppm tFSH tFSL Figure 5. FailSafe Reference Switching Behavior Time Document Number: 38-07304 Rev. L Page 5 of 16 5 Page CY23FS04 Switching Waveforms Figure 8. Duty Cycle Duty Cycle - tDC = t1 / t2 VDD/2 VDD/2 t1 t2 VDD/2 Figure 9. Input Slew Rate 70% 30% t SR(I) 70% 30% t SR(I) 80% 20% Figure 10. Output Slew Rate 80% 20% tSR(O) tSR(O) Figure 11. Output to Output Skew and Intrabank Skew VDD/2 VDD 0V VDD 0V VDD 0V FBK, Part 1 FBK, Part 2 VDD/2 tSK Figure 12. Part to Part Skew VDD/2 VDD/2 tSK(PP) Document Number: 38-07304 Rev. *L Page 11 of 16 11 Page

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Número de pieza	Descripción	Fabricantes
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