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PDF ISL78302 Data sheet ( Hoja de datos )
| Número de pieza | ISL78302 | |
| Descripción | Dual LDO | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Dual LDO with Low Noise, High Performance and Low IQ
ISL78302
Features
ISL78302 is a high performance dual LDO capable of sourcing
300mA current from each output. It has a low standby current
and is stable with output capacitance of 1µF to 10µF with ESR of
up to 200mΩ.
The device integrates an individual Power-On-Reset (POR) function for
each output. The POR delay for VO2 can be externally programmed by
connecting a timing capacitor to the CPOR pin. The POR delay for VO1 is
internally fixed at approximately 2ms. A reference bypass pin is also
provided for connecting a noise filtering capacitor for low noise and
high-PSRR applications.
The quiescent current is typically only 47µA with both LDOs
enabled and active. Separate enable pins control each individual
LDO output. When both enable pins are low, the device is in
shutdown, typically drawing less than 0.5µA.
The part operates down to 2.3V and up to 6.5V input. The typical
output voltage can be as low as 1.2V and as high as 3.3V for
each regulator. Please refer to the ordering information section
for standard options. Other voltage selections are available upon
request.
• Integrates Two 300mA High Performance LDOs
• Excellent Transient Response to Large Current Steps
• ±1.8% Accuracy Over All Operating Conditions
• Excellent Load Regulation: < 0.1% Voltage Change Across Full
Range of Load Current
• Extremely Low Quiescent Current: 47µA (Both LDOs Active)
• Wide Input Voltage Capability: 2.3V to 6.5V
• Low Dropout Voltage: Typically 300mV @ 300mA
• Low Output Noise: Typically 37µVRMS @ 100µA (1.5V)
• Stable with 1µF to 10µF Ceramic Capacitors
• Separate Enable and POR Pins for Each LDO
• Soft-start and Staged Turn-on to Limit Input Current Surge
During Enable
• Current Limit and Over-temperature Protection
• Tiny 10 Lead 3mm x 3mm DFN Package
• TS16949 Compliant
The ISL78302 is both AEC - Q100 rated and fully TS16949
compliant. The ISL78302 is rated for the automotive
temperature range (-40°C to +105°C).
• AEC - Q100 Tested
• Pb-free (RoHS Compliant)
Applications
• Radio Receivers
• Camera Modules
• GPS/Navigation
• Infotainment Systems
Typical Application
VIN (2.3 TO 6.5V)
ON
ENABLE1
OFF ON
ENABLE2
OFF
ISL78302
1
VIN
10
VO1
2
EN1
9
VO2
3
EN2
4
CBYP
POR2
POR1
8
7
5
CPOR
6
GND
C1 C2 C3
C4 C5
VOUT1
VOUT2 OK
VOUT2 TOO LOW
VOUT1 OK
VOUT2
RESET2
(200ms DELAY,
C3 = 0.01µF)
RESET1
VOUT1 TOO LOW (2ms DELAY)
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C1, C4, C5: 1µF X5R CERAMIC CAPACITOR
C2: 0.01µF X7R CERAMIC CAPACITOR
C3: 0.01µF X7R CERAMIC CAPACITOR
January 28, 2011
FN7696.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL78302
Electrical Specifications Unless otherwise noted, all parameters are guaranteed over the operational supply voltage and
temperature range of the device as follows: TA = -40°C to +105°C; VIN = (VO + 0.5V) to 6.5V with a minimum VIN of 2.3V; CIN = 1µF; CO = 1µF;
CBYP = 0.01µF; CPOR = 0.01µF. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 8) TYP
MAX
(Note 8)
UNITS
Output Noise Voltage
IO = 100µA, VO = 1.5V, TA = +25°C, CBYP = 0.01µF
BW = 10Hz to 100kHz
37 µVRMS
DEVICE START-UP CHARACTERISTICS
Device Enable Time
tEN Time from assertion of the ENx pin to when the output
voltage reaches 95% of the VO(nom)
250 500
µs
LDO Soft-Start Ramp Rate
tSSR Slope of linear portion of LDO output voltage ramp during
start-up
30 60
µs/V
EN1, EN2 PIN CHARACTERISTICS
Input Low Voltage
VIL
Input High Voltage
VIH
Input Leakage Current
IIL, IIH
Pin Capacitance
CPIN
POR1, POR2 PIN CHARACTERISTICS
Informative
-0.3
1.35
0.5
VIN + 0.3
0.1
5
V
V
µA
pF
POR1, POR2 Thresholds
POR1 Delay
POR2 Delay
POR1, POR2 Pin Output Low
Voltage
VPOR+
VPOR-
tP1LH
tP1HL
tP2LH
tP2HL
VOL
As a percentage of nominal output voltage
CPOR = 0.01µF
@ IOL = 1.0mA
91 94
87 90
0.5 2.0
25
100 200
25
97
93
3.2
300
0.2
%
%
ms
µs
ms
µs
V
POR1, POR2 Pin Internal Pull-Up
Resistance
RPOR
78 100 180
kΩ
NOTES:
7. VOx = 0.98*VOx(NOM); Valid for VOx greater than 1.85V.
8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
EN1
EN2
tEN
VPOR+
VO1
VO2
www.DataSheet4U.com
POR1
POR2
tP1LH
tP2LH
VPOR-
VPOR+
<tP1HL
<tP2HL
tP1HL
tP2HL
VPOR-
FIGURE 1. TIMING PARAMETER DEFINITION
5 FN7696.0
January 28, 2011
5 Page 
Package Outline Drawing
L10.3x3C
10 LEAD DUAL FLAT PACKAGE (DFN)
Rev 2, 09/09
3.00
6
PIN 1
INDEX AREA
(4X) 0.10 C B
TOP VIEW
ISL78302
A
B
10
6
6
PIN #1 INDEX AREA
1
2
10 x 0.25
1.64
BOTTOM VIEW
10x 0.40
5
(4X) 0.10 M C B
PACKAGE
OUTLINE
(10x 0.25)
(10 x 0.60)
(8x 0.50)
1.64
TYPICAL RECOMMENDED LAND PATTERN
www.DataSheet4U.com
11
0.20
SIDE VIEW
SEE DETAIL "X"
0.10 C
C
BASE PLANE
SEATING PLANE
0.08 C
C 0.20 REF
5
0.05
NOTES:
DETAIL "X"
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension b applies to the metallized terminal and is measured
between 0.18mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
7. COMPLAINT TO JEDEC MO-229-WEED-3 except for E-PAD
dimensions.
FN7696.0
January 28, 2011
11 Page | ||
| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet ISL78302.PDF ] | |
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