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PDF LTC2752 Data sheet ( Hoja de datos )
| Número de pieza | LTC2752 | |
| Descripción | Dual16-Bit SoftSpan IOUT DACs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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Features
n Program or Pin-Strap Six Output Ranges
0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V
n Maximum 16-Bit INL Error: ±1 LSB over
Temperature
n Guaranteed Monotonic over Temperature
n Glitch Impulse 0.6nV•s (3V), 2.2nV•s (5V)
n Serial Readback of All On-Chip Registers
n 1μA Maximum Supply Current
n 2.7V to 5.5V Single-Supply Operation
n 16-Bit Settling Time: 2µs
n Voltage-Controlled Offset and Gain Trims
n Clear and Power-On-Reset to 0V Regardless of
Output Range
n 48-Pin 7mm × 7mm LQFP Package
Applications
n High Resolution Offset and Gain Adjustment
n Process Control and Industrial Automation
n Automatic Test Equipment
n Data Acquisition Systems
LTC2752www.DataSheet4U.com
Dual16-Bit
SoftSpan IOUT DACs
Description
The LTC®2752 is a dual 16-bit multiplying serial-input,
current-output digital-to-analog converter. It operates from
a single 3V to 5V supply and is guaranteed monotonic
over temperature. The LTC2752A provides full 16-bit
performance (±1LSB INL and DNL, max) over temperature
without any adjustments. This SoftSpan™ DAC offers
six output ranges (up to ±10V) that can be programmed
through the 3-wire SPI serial interface, or pinstrapped for
operation in a single range.
Any on-chip register (including DAC output-range set-
tings) can be read for verification in just one instruction
cycle; and if you change register content, the altered
register will be automatically read back during the next
instruction cycle.
Voltage-controlled offset and gain adjustments are also
provided; and the power-on reset circuit and CLR pin both
reset the DAC outputs to 0V regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178.
Typical Application
Dual 16-Bit VOUT DAC with Software-Selectable Ranges
REFERENCE
5V
VDD
SPI with READBACK
GND
DAC A
LTC2752
DAC B
RFBA
IOUT1A
IOUT2A
–
+
VOSADJA
RFBB
IOUT1B
IOUT2B
–
+
VOSADJB
VOUTA
VOUTB
ALL AMPLIFIERS 1/2 LT1469
REFERENCE
5V
2752 TA01
Integral Nonlinearity (INL)
1.0
0.8 ±10V RANGE
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
49152 65535
2752 TA01b
2752f
1 page  
LTC2752www.DataSheet4U.com
t iming Characteristics
otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
t8 CS/LD High to SCK Positive Edge
t9 SRO Propagation Delay
t10 CLR Pulse Width Low
t11 LDAC Pulse Width Low
t12 CLR Low to RFLAG Low
t13 CS/LD High to RFLAG high
SCK Frequency
The l denotes specifications that apply over the full operating temperature range,
CONDITIONS
CLOAD = 10pF
CLOAD = 10pF (Note 13)
CLOAD = 10pF (Note 13)
50% Duty Cycle (Note 14)
MIN TYP MAX UNITS
l5
ns
l 26 ns
l 60
ns
l 20
ns
l 70 ns
l 60 ns
l 25 MHz
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Calculation from feedback resistance and IOUT1 leakage current
specifications; not production tested. In most applications, unipolar zero-
scale error is dominated by contributions from the output amplifier.
Note 4: Input resistors measured from RINX to RCOMX; feedback resistors
measured from RCOMX to REFX.
Note 5: DAC input resistance is independent of code.
Note 6: Parallel combination of the resistances from the specified pin to
IOUT1X and from the specified pin to IOUT2X.
Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0015% settling time
of 1.7μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 74, Component and Measurement Advances
Ensure 16-Bit DAC Settling Time.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1468; CFB = 50pF.
Note 9. Full-scale transition; REF = 0V.
Note 10. Analog Crosstalk is defined as the AC voltage ratio VOUTB/VREFA,
expressed in dB. REFB is grounded, and DAC B is set to 0V-5V span and
zero-, mid- or full- scale code. VREFA is a 3VRMS, 1kHz sine wave.
Note 11. REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1469.
Note 12. Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and
B = bandwidth (Hz). 0V to 5V Range; zero-, mid-, or full- scale.
Note 13. Guaranteed by design, not subject to test.
Note 14. When using SRO, maximum SCK frequency fMAX is limited by
SRO propagation delay t9 as follows:
( )
fMAX
=
2
1
t9 +
tS
,
where
tS
is
the
setup
time
of
the
receiving
device.
2752f
5 Page 
Block Diagram
LTC2752www.DataSheet4U.com
16
VDD
RINA (5, 6)
4 GEADJA
3 RCOMA
2.56M
20k
20k
2.56M
20k
20k
(31, 32) RINB
GEADJB 33
RCOMB 34
REFA (1, 2)
ROFSA (47, 48)
RFBA (45, 46)
44 IOUT1A
8 IOUT2AS
9 IOUT2AF
43 VOSADJA
DAC A
16-BIT WITH
SPAN SELECT
16 CODE REGISTERS
DAC REG INPUT REG
3 SPAN REGISTERS
DAC REG INPUT REG
CODE REGISTERS
16
INPUT REG DAC REG
SPAN REGISTERS
INPUT REG DAC REG
3
DAC B
16-BIT WITH
SPAN SELECT
(35, 36) REFB
(37, 38) ROFSB
(39, 40) RFBB
IOUT1B 41
IOUT2BS 29
IOUT2BF 28
VOSADJB 42
POWER-ON
RESET
CONTROL AND READBACK LOGIC
GND (7, 10, 15, 17, 18, 27, 30) M-SPAN S0 S1 S2 RFLAG CLR CS/LD SDI SCK LDAC SRO
22 23 24 25 20
19 11 12 13 26 14
2752 BD
2752f
11
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2752.PDF ] | |
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