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PDF LTC2753 Data sheet ( Hoja de datos )
| Número de pieza | LTC2753 | |
| Descripción | Dual Current Output 12-/14-/16-Bit SoftSpan DACs | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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LTC2753
Dual Current Output
12-/14-/16-Bit SoftSpan
DACs with Parallel I/O
FEATURES
■ Six Programmable Output Ranges
Unipolar: 0V to 5V, 0V to 10V
Bipolar: ±5V, ±10V, ±2.5V, –2.5V to 7.5V
www.DataSh■eetM4Ua.cxoimmum 16-Bit INL Error: ±1 LSB over Temperature
■ Low 1μA (Maximum) Supply Current
■ Guaranteed Monotonic over Temperature
■ Low Glitch Impulse 1nV•s
■ 2.7V to 5.5V Single Supply Operation
■ 2μs Settling Time to ±1 LSB
■ Parallel Interface with Readback of All Registers
■ Asynchronous CLR Pin Clears DAC Outputs to 0V in
Any Output Range
■ Power-On Reset to 0V
■ 48-Pin 7mm × 7mm QFN Package
APPLICATIONS
■ High Resolution Offset and Gain Adjustment
■ Process Control and Industrial Automation
■ Automatic Test Equipment
■ Data Acquisition Systems
DESCRIPTION
The LTC®2753 is a family of dual 12-, 14-, and 16-bit
multiplying parallel-input, current-output DACs. These
DACs operate from a single 2.7V to 5.5V supply and are all
guaranteed monotonic over temperature. The LTC2753A-16
provides 16-bit performance (±1LSB INL and DNL) over
temperature without any adjustments. These SoftSpan™
DACs offer six output ranges—two unipolar and four
bipolar—that can be programmed through the parallel
interface, or pinstrapped for operation in a single range.
The LTC2753 DACs use a bidirectional input/output parallel
interface that allows readback of any on-chip register. A
power-on reset circuit resets the DAC outputs to 0V when
power is initially applied. A logic low on the CLR pin asyn-
chronously clears the DACs to 0V in any output range.
The parts are specified over commercial and industrial
temperature ranges.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the
property of their respective owners.
TYPICAL APPLICATION
Dual 16-Bit VOUT DAC with Software-Selectable Ranges
VREF
5V
ROFSA 47
RIN 2
LTC2753-16
46 RFBA
+
1/2 LT1469
–
150pF
RCOM 1
R1
REFA 48
R2
DAC A
15pF
45 IOUT1A
4 IOUT2A
44 RVOSA
–
1/2 LT1469
+
VOUTA
REFB 39
43 RVOSB
32 IOUT2B
+
DAC B
ROFSB 40
SPAN I/O
3
16
DATA I/O
I/O PORT
I/O PORT
42 IOUT1B
15pF
41 RFBB
1/2 LT1469
–
VOUTB
2753 TA01
LTC2753-16 Integral Nonlinearity (INL)
1.0
VDD = 5V
0.8 VREF = 5V
0.6 ±10V RANGE
0.4
0.2
0.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
16384
32768
CODE
25°C
90°C
–45°C
49152 65535
2753 TA01b
2753f
1
1 page  
LTC2753
TIMING CHARACTERISTICS
otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
t17 UPD Valid to I/O Propagation Delay
t18 D/S Valid to READ Rising Edge
t19 READ Rising Edge to UPD Rising Edge
t20 UPD Falling Edge to READ Falling Edge
t22 READ Falling Edge to UPD Rising Edge
t23 I/O Bus Hi-Z to READ Rising Edge
www.DataShte24et4U.com READ Falling Edge to I/O Bus Active
CLR Timing
t25 CLR Pulse Width Low
The ● denotes specifications that apply over the full operating temperature range,
CONDITIONS
CL = 10pF
(Note 10)
No Update
No Update
(Note 10)
(Note 10)
(Note 10)
MIN TYP MAX UNITS
● 26 ns
●7
ns
●0
ns
●0
ns
●7
ns
●0
ns
● 20
ns
● 15
ns
VDD = 2.7V to 3.3V
Write and Update Timing
t1 I/O Valid to WR Rising Edge Set-Up
t2 I/O Valid to WR Rising Edge Hold
t3 WR Pulse Width Low
t4 UPD Pulse Width High
t5 UPD Falling Edge to WR Falling Edge
t6 WR Rising Edge to UPD Rising Edge
t7 D/S Valid to WR Falling Edge Set-Up Time
t8 WR Rising Edge to D/S Valid Hold Time
t9 A1-A0 Valid to WR Falling Edge Setup Time
t10 WR Rising Edge to A1-A0 Valid Hold Time
t11 A1-A0 Valid to UPD Rising Edge Setup Time
t12 UPD Falling Edge to A1-A0 Valid Hold Time
Readback Timing
t13 WR Rising Edge to Read Rising Edge
t14 Read Falling Edge to WR Falling Edge
t15 Read Rising Edge to I/O Propagation Delay
t26 A1-A0 Valid to READ Rising Edge Setup Time
t27 READ Falling to A1-A0 Valid Hold Time
t17 UPD Valid to I/O Propagation Delay
t18 D/S Valid to Read Rising Edge
t19 Read Rising Edge to UPD Rising Edge
t20 UPD Falling Edge to Read Falling Edge
No Data Shoot-Through
(Note 10)
(Note 10)
CL = 10pF
(Note 10)
CL = 10pF
(Note 10)
No Update
No Update
● 15
● 15
● 30
● 30
●0
●0
●7
●7
●7
●0
● 15
● 15
● 10
● 35
●
● 35
●0
●
● 12
●0
●0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
53 ns
ns
ns
43 ns
ns
ns
ns
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5 Page 
LTC2753
PIN FUNCTIONS
output the contents of the selected register (see Table
1). For single-span operation, readback of the span I/O
pins is disabled.
UPD (Pin 36): Update and Buffer Select Pin. When READ
is held low and UPD is asserted high, the contents of the
addressed DAC’s input registers (both data and span) are
copied into their respective DAC registers. The output of the
DAC is updated, reflecting the new DAC register values.
www.DataShWeeht4eUn.cRomEAD is held high, the update function is disabled
and the UPD pin functions as a buffer selector—logic low
to select the input register, high to select the DAC register.
See Readback in the Operation section.
WR (Pin 37): Active Low Write Pin. A Write operation cop-
ies the data present on the data or span I/O pins (D0-D15
or S0-S2, respectively) into the associated input register.
When READ is high, the Write function is disabled.
S1 (Pin 38): Span I/O Bit 1. Pins S0, S1 and S2 are used
to program and to read back the output ranges of the
DACs.
REFB (Pin 39): Reference Input for DAC B. The impedance
looking into this pin is 10k to ground. For normal opera-
tion tie to the output of the reference inverting amplifier.
Typically –5V; accepts up to ±15V.
ROFSB (Pin 40): Bipolar Offset Network for DAC B. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RIN (Pin 2). The
impedance looking into this pin is 20k to ground.
RFBB (Pin 41): DAC B Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifier
for DAC B (see Typical Applications). The DAC output
current from IOUT1B flows through the feedback resistor
to the RFBB pin. The impedance looking into this pin is
10k to ground.
IOUT1B (Pin 42): DAC B Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifier for DAC B (see Typical Applications).
RVOSB (Pin 43): DAC B Offset Adjust. Nominal input range
is ±5V. The impedance looking into this pin is 1M to ground.
If not used, tie RVOSB to ground.
RVOSA (Pin 44): DAC A Offset Adjust. Nominal input range
is ±5V. The impedance looking into this pin is 1M to ground.
If not used, tie RVOSA to ground.
IOUT1A (Pin 45): DAC A Current Output. This pin is a virtual
ground when the DAC is operating and should reside at
0V. For normal operation tie to the negative input of the I/V
converter amplifier for DAC A (see Typical Applications).
RFBA (Pin 46): DAC A Feedback Resistor. For normal
operation tie to the output of the I/V converter amplifier
for DAC A (see Typical Applications). The DAC output
current from IOUT1A flows through the feedback resistor
to the RFBA pin. The impedance looking into this pin is
10k to ground.
ROFSA (Pin 47): Bipolar Offset Network for DAC A. This
pin provides the translation of the output voltage range for
bipolar spans. Accepts up to ±15V; for normal operation
tie to the positive reference voltage at RIN (Pin 2). The
impedance looking into this pin is 20k to ground.
REFA (Pin 48): Reference Input for DAC A, and connec-
tion for internal reference inverting resistor R2. The 20k
resistor R2 is connected internally from RCOM to REFA. For
normal operation tie this pin to the output of the reference
inverting amplifier (see Typical Applications). Typically –5V;
accepts up to ±15V. The impedance looking into this pin
is 10k to ground (RIN and RCOM floating).
Exposed Pad (Pin 49): Ground. The Exposed Pad must
be soldered to the PCB.
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11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet LTC2753.PDF ] | |
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