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PDF LTC2259-16 Data sheet ( Hoja de datos )
| Número de pieza | LTC2259-16 | |
| Descripción | 80Msps Ultralow Power 1.8V ADC | |
| Fabricantes | Linear Technology | |
| Logotipo |  |
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FEATURES
n 73.1dB SNR
n 88dB SFDR
n Low Power: 89mW
n Single 1.8V Supply
n CMOS, DDR CMOS or DDR LVDS Outputs
n Selectable Input Ranges: 1VP-P to 2VP-P
n 800MHz Full-Power Bandwidth S/H
n Optional Data Output Randomizer
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n 40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
LTC2259-16www.DataSheet4U.com
16-Bit, 80Msps Ultralow
Power 1.8V ADC
DESCRIPTION
The LTC®2259-16 is a sampling 16-bit A/D converter de-
signed for digitizing high frequency, wide dynamic range
signals. It is perfect for demanding communications ap-
plications with AC performance that includes 73.1dB SNR
and 88dB spurious free dynamic range (SFDR). Ultralow
jitter of 0.17psRMS allows undersampling of IF frequencies
with excellent noise performance.
DC specs include ±4LSB INL (typical) and ±0.5LSB DNL
(typical).
The digital outputs can be either full-rate CMOS, double-
data rate CMOS, or double-data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENC– inputs may be driven differentially or
single ended with a sine wave, PECL, LVDS, TTL or CMOS
inputs. An optional clock duty cycle stabilizer allows high
performance at full speed for a wide range of clock duty
cycles.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
VDD
ANALOG
INPUT
+
INPUT
S/H
–
16-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
80MHz
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
GND
OUTPUT
DRIVERS
1.2V
TO 1.8V
OVDD
D15
• CMOS
• OR
• LVDS
D0
OGND
225916 TA01a
2-Tone FFT, fIN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20 30
FREQUENCY (MHz)
40
225916 TA01b
225916f
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1 page  
LTC2259-16www.DataSheet4U.com
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V
IOH Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT Output Capacitance
(Note 8)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE-DATA RATE)
200 Ω
l –10
10 μA
4 pF
OVDD = 1.8V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.5V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.2V
VOH High Level Output Voltage
VOL Low Level Output Voltage
DIGITAL DATA OUTPUTS (LVDS MODE)
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
l 1.750
l
1.790
0.010
1.488
0.010
1.185
0.010
0.050
V
V
V
V
V
V
VOD Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
l 247
350
454 mV
100Ω Differential Load, 1.75mA Mode
175 mV
VOS Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l 1.125
1.250
1.250
1.375
V
V
RTERM On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100 Ω
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
SYMBOL PARAMETER
CONDITIONS
MIN TYP
MAX
UNITS
CMOS Output Modes: Full Data Rate and Double-Data Rate
VDD
OVDD
IVDD
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
(Note 10)
(Note 10)
DC Input
Sine Wave Input
l 1.7
1.8
1.9
l 1.1
1.9
l 49.2 58.1
50.2
V
V
mA
mA
IOVDD
PDISS
Digital Supply Current
Power Dissipation
LVDS Output Mode
Sine Wave Input, OVDD=1.2V
DC Input
Sine Wave Input, OVDD=1.2V
2.5 mA
l
89 105
mW
93 mW
VDD
OVDD
IVDD
IOVDD
PDISS
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
(0VDD = 1.8V)
Power Dissipation
(Note 10)
(Note 10)
Sine Wave Input
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
Sine Input, 1.75mA Mode
Sine Input, 3.5mA Mode
l 1.7
1.8
1.9
l 1.7
1.9
l 53.8 63.5
l 20.7 26
l 40.5 47.8
l 134 161
l 170 201
V
V
mA
mA
mA
mW
mW
All Output Modes
PSLEEP
PNAP
PDIFFCLK
Sleep Mode Power
Nap Mode Power
Power Increase with Differential Encode Mode Enabled
(No increase for Nap or Sleep Modes)
0.5 mW
9 mW
10 mW
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LTC2259-16www.DataSheet4U.com
PIN FUNCTIONS
PINS THAT ARE THE SAME FOR ALL DIGITAL OUTPUT
MODES
AIN+ (Pin 1): Positive Differential Analog Input.
AIN– (Pin 2): Negative Differential Analog Input.
GND (Pin 3, Exposed Pad Pin 41): ADC Power Ground.
REFH (Pins 4, 5): ADC High Reference. Bypass to Pins
6, 7 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
REFL (Pins 6, 7): ADC Low Reference. Bypass to Pins
4, 5 with a 2.2μF ceramic capacitor and to ground with a
0.1μF ceramic capacitor.
PAR/SER (Pin 8): Programming Mode Selection Pin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to VDD to enable the
parallel programming mode where CS, SCK, SDI become
parallel logic inputs that control a reduced set of the A/D
operating modes. PAR/SER should be connected directly
to ground or the VDD of the part and not be driven by a
logic signal.
VDD (Pins 9, 10, 40): 1.8V Analog Power Supply. Bypass
to ground with 0.1μF ceramic capacitors. Pins 9 and 10
can share a bypass capacitor.
ENC+ (Pin 11): Encode Input. Conversion starts on the
rising edge.
ENC– (Pin 12): Encode Complement Input. Conversion
starts on the falling edge.
CS (Pin 13): In serial programming mode, (PAR/SER =
0V), CS is the serial interface chip select input. When
CS is low, SCK is enabled for shifting data on SDI into
the mode control registers. In the parallel programming
mode (PAR/SER = VDD), CS controls the clock duty cycle
stabilizer. When CS is low, the clock duty cycle stabilizer is
turned off. When CS is high, the clock duty cycle stabilizer
is turned on. CS can be driven with 1.8V to 3.3V logic.
SCK (Pin 14): In serial programming mode, (PAR/SER =
0V), SCK is the serial interface clock input. In the parallel
programming mode (PAR/SER = VDD), SCK controls the
digital output mode. When SCK is low, the full-rate CMOS
output mode is enabled. When SCK is high, the double-
data rate LVDS output mode (with 3.5mA output current)
is enabled. SCK can be driven with 1.8V to 3.3V logic.
SDI (Pin 15): In serial programming mode, (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI is
clocked into the mode control registers on the rising edge
of SCK. In the parallel programming mode (PAR/SER =
VDD), SDI can be used to power down the part. When SDI
is low, the part operates normally. When SDI is high, the
part enters sleep mode. SDI can be driven with 1.8V to
3.3V logic.
SDO (Pin 16): In serial programming mode, (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control registers
and can be latched on the falling edge of SCK. SDO is an
open-drain NMOS output that requires an external 2k
pull-up resistor to 1.8V-3.3V. If read back from the mode
control registers is not needed, the pull-up resistor is not
necessary and SDO can be left unconnected. In the parallel
programming mode (PAR/SER = VDD), SDO is not used
and should not be connected.
OGND (Pin 25): Output Driver Ground.
OVDD (Pin 26): Output Driver Supply. Bypass to ground
with a 0.1μF ceramic capacitor.
VCM (Pin 37): Common Mode Bias Output, Nominally
Equal to VDD/2. VCM should be used to bias the common
mode of the analog inputs. Bypass to ground with a 0.1μF
ceramic capacitor.
VREF (Pin 38): Reference Voltage Output. Bypass to ground
with a 1μF ceramic capacitor, nominally 1.25V.
SENSE (Pin 39): Reference Programming Pin. Connecting
SENSE to VDD selects the internal reference and a ±1V input
range. Connecting SENSE to ground selects the internal
reference and a ±0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • VSENSE.
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11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet LTC2259-16.PDF ] | |
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