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PDF LTC2259-12 Data sheet ( Hoja de datos )

Número de pieza LTC2259-12
Descripción (LTC22xx-12) 125/105/80Msps Ultralow Power 1.8V ADCs
Fabricantes Linear Technology 
Logotipo Linear Technology Logotipo



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No Preview Available ! LTC2259-12 Hoja de datos, Descripción, Manual

FEATURES
www.datasheet4u.com
n 70.8dB SNR
n 85dB SFDR
n Low Power: 124mW/103mW/87mW
n Single 1.8V Supply
n CMOS, DDR CMOS or DDR LVDS Outputs
n Selectable Input Ranges: 1VP-P to 2VP-P
n 800MHz Full-Power Bandwidth S/H
n Optional Data Output Randomizer
n Optional Clock Duty Cycle Stabilizer
n Shutdown and Nap Modes
n Serial SPI Port for Configuration
n Pin Compatible 14-Bit and 12-Bit Versions
n 40-Pin (6mm × 6mm) QFN Package
APPLICATIONS
n Communications
n Cellular Base Stations
n Software Defined Radios
n Portable Medical Imaging
n Multi-Channel Data Acquisition
n Nondestructive Testing
LTC2261-12
LTC2260-12/LTC2259-12
12-Bit, 125/105/80Msps
Ultralow Power 1.8V ADCs
DESCRIPTION
The LTC®2261-12/LTC2260-12/LTC2259-12 are sam-
pling 12-bit A/D converters designed for digitizing high
frequency, wide dynamic range signals. They are perfect
for demanding communications applications with AC
performance that includes 70.8dB SNR and 85dB spurious
free dynamic range (SFDR). Ultralow jitter of 0.17psRMS
allows undersampling of IF frequencies with excellent
noise performance.
DC specs include ±0.3LSB INL (typical), ±0.1LSB DNL
(typical) and no missing codes over temperature. The
transition noise is a low 0.3LSBRMS.
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
The ENC+ and ENCinputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
L, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
VDD
ANALOG
INPUT
+
INPUT
S/H
12-BIT
PIPELINED
ADC CORE
CORRECTION
LOGIC
125MHz
CLOCK
CLOCK/DUTY
CYCLE
CONTROL
GND
OUTPUT
DRIVERS
1.2V
TO 1.8V
OVDD
D11
• CMOS
• OR
• LVDS
D0
OGND
226112 TA01a
2-Tone FFT, fIN = 70MHz and 75MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10 20 30 40 50 60
FREQUENCY (MHz)
226112 TA01b
226112f
1

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LTC2259-12 pdf
LTC2261-12
LTC2260-12/LTC2259-12
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC)
wwwD.difaftearsehnetieatl4Eun.ccoodme Mode (ENCNot Tied to GND)
VID Differential Input Voltage
VICM Common Mode Input Voltage
VIN Input Voltage Range
(Note 8)
Internally Set
Externally Set (Note 8)
ENC+, ENCto GND
l 0.2
1.2
l 1.1
1.6
l 0.2
3.6
V
V
V
V
RIN Input Resistance
CIN Input Capacitance
Single-Ended Encode Mode (ENCTied to GND)
(See Figure 10)
(Note 8)
10 kΩ
3.5 pF
VIH High Level Input Voltage
VIL Low Level Input Voltage
VIN Input Voltage Range
VDD = 1.8V
VDD = 1.8V
ENC+ to GND
l 1.2
l
l0
V
0.6 V
3.6 V
RIN Input Resistance
CIN Input Capacitance
DIGITAL INPUTS (CS, SDI, SCK)
(See Figure 11)
(Note 8)
30 kΩ
3.5 pF
VIH High Level Input Voltage
VIL Low Level Input Voltage
IIN Input Current
VDD = 1.8V
VDD = 1.8V
VIN = 0V to 3.6V
l 1.3
l
l –10
V
0.6 V
10 μA
CIN Input Capacitance
(Note 8)
SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO is Used)
3 pF
ROL Logic Low Output Resistance to GND VDD = 1.8V, SDO = 0V
IOH Logic High Output Leakage Current
SDO = 0V to 3.6V
COUT Output Capacitance
(Note 8)
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
200 Ω
l –10
10 μA
4 pF
OVDD = 1.8V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.5V
VOH High Level Output Voltage
VOL Low Level Output Voltage
OVDD = 1.2V
VOH High Level Output Voltage
VOL Low Level Output Voltage
DIGITAL DATA OUTPUTS (LVDS MODE)
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
IO = –500μA
IO = 500μA
l 1.750
l
1.790
0.010
1.488
0.010
1.185
0.010
0.050
V
V
V
V
V
V
VOD Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
l 247
350
454
mV
100Ω Differential Load, 1.75mA Mode
175 mV
VOS Common Mode Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
l 1.125
1.250
1.250
1.375
V
V
RTERM On-Chip Termination Resistance
Termination Enabled, OVDD = 1.8V
100 Ω
226112f
5

5 Page





LTC2259-12 arduino
LTC2261-12
LTC2260-12/LTC2259-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2261-12: IOVDD vs Sample
Rate, 5MHz Sine Wave Input,
–1dB, 5pF on Each Data Output
www.data4s5heet4u.com
40 3.5mA LVDS
35
30
25
1.75mA LVDS
20
15
10
5
0
0
1.8V CMOS
1.2V CMOS
25 50 75 100 125
SAMPLE RATE (Msps)
226112 G14
LTC2261-12: SNR vs SENSE,
fIN = 5MHz, –1dB
72
71
70
69
68
67
66
0.6 0.7
0.8 0.9 1 1.1
SENSE PIN (V)
1.2 1.3
226112 G15
LTC2260-12: Integral Nonlinearity
(INL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
226112 G21
LTC2260-12: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
1024
2048
3072
OUTPUT CODE
4096
226112 G22
LTC2261-12: SNR vs Sample Rate
and Digital Output Mode,
30MHz Sine Wave Input, –1dB
72
71 LVDS
CMOS
70
DDR CMOS
69
68
67
0
25 50 75 100
SAMPLE RATE (Msps)
125
226112 G18
LTC2260-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20 30 40
FREQUENCY (MHz)
50
226112 G23
LTC2260-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20 30 40
FREQUENCY (MHz)
50
226112 G24
LTC2260-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20 30 40
FREQUENCY (MHz)
50
226112 G25
LTC2260-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
10 20 30 40
FREQUENCY (MHz)
50
226112 G26
226112f
11

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