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PDF MAX17043 Data sheet ( Hoja de datos )
| Número de pieza | MAX17043 | |
| Descripción | Low-Cost 1S/2S Fuel Gauges | |
| Fabricantes | Maxim Integrated Products | |
| Logotipo |  |
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19-4811; Rev 1; 4/10
www.DataSheet4U.com
EVAALVUAAILTAIOBNLEKIT
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
General Description
The MAX17043/MAX17044 are ultra-compact, low-cost,
host-side fuel-gauge systems for lithium-ion (Li+) batter-
ies in handheld and portable equipment. The MAX17043
is configured to operate with a single lithium cell and the
MAX17044 is configured for a dual-cell 2S pack.
The MAX17043/MAX17044 use a sophisticated Li+ bat-
tery-modeling scheme, called ModelGauge™ to track
the battery’s relative state-of-charge (SOC) continuously
over a widely varying charge/discharge profile. Unlike
traditional fuel gauges, the ModelGauge algorithm elim-
inates the need for battery relearn cycles and an exter-
nal current-sense resistor. Temperature compensation
is possible in the application with minimal interaction
between a µC and the device.
A quick-start mode provides a good initial estimate of
the battery’s SOC. This feature allows the IC to be
located on system side, reducing cost and supply
chain constraints on the battery. Measurement and esti-
mated capacity data sets are accessed through an I2C
interface. The MAX17043/MAX17044 are available in a
small, 2mm x 3mm, 8-pin TDFN lead-free package.
Applications
Smartphones
Portable DVD Players
MP3 Players
GPS Systems
Digital Still Cameras
Digital Video Cameras
Handheld and Portable
Applications
ModelGauge is a trademark of Maxim Integrated Products, Inc.
Features
♦ Host-Side or Battery-Side Fuel Gauging
1 Cell (MAX17043)
2 Cell (MAX17044)
♦ Precision Voltage Measurement
±12.5mV Accuracy to 5.00V (MAX17043)
±30mV Accuracy to 10.00V (MAX17044)
♦ Accurate Relative Capacity (RSOC) Calculated
from ModelGauge Algorithm
♦ No Offset Accumulation on Measurement
♦ No Full-to-Empty Battery Relearning Necessary
♦ No Sense Resistor Required
♦ External Alarm/Interrupt for Low-Battery Warning
♦ 2-Wire Interface
♦ Low Power Consumption
♦ Tiny, Lead-Free, 8-Pin, 2mm x 3mm TDFN
Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX17043G+U
-20°C to +70°C
8 TDFN-EP*
MAX17043G+T
-20°C to +70°C
8 TDFN-EP*
MAX17044G+U
-20°C to +70°C
8 TDFN-EP*
MAX17044G+T
-20°C to +70°C
8 TDFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
*EP = Exposed pad.
Simplified Operating Circuit
1kΩ
Li+
PROTECTION
CIRCUIT
1µF
CELL
VDD
ALRT
MAX17043
MAX17044
QSTRT
CTG SDA
GND SCL
EP
150Ω
4.7kΩ
SYSTEM
µP
INTERRUPT
I2C BUS
MASTER
10nF
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
www.DataSheet4U.com
Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
Pin Configuration
TOP VIEW
SDA SCL QSTRT ALRT
8765
MAX17043
MAX17044
+
1 234
CTG CELL VDD GND
TDFN
(2mm × 3mm)
Pin Description
PIN NAME
FUNCTION
1
CTG
Connect to Ground. Connect to VSS during normal operation.
2 CELL Battery Voltage Input. The voltage of the cell pack is measured through this pin.
3
VDD
Power-Supply Input. 2.5V to 4.5V input range. Connect to system power through a decoupling
network. Connect a 10nF typical decoupling capacitor close to pin.
4
GND
Ground. Connect to the negative power rail of the system.
5
ALRT
Alert Output. Active-low interrupt signaling low state of charge. Connect to interrupt input of the
system microprocessor.
6 QSTRT Quick-Start Input. Allows reset of the device through hardware. Connect to GND if not used.
7 SCL Serial-Clock Input. Input only 2-wire clock line. Connect this pin to the CLOCK signal of the 2-wire
interface. This pin has a 0.2µA typical pulldown to sense disconnection.
8
SDA
Serial-Data Input/Output. Open-drain 2-wire data line. Connect this pin to the DATA signal of the
2-wire interface. This pin has a 0.2µA typical pulldown to sense disconnection.
— EP Exposed Pad. Connect to GND.
_______________________________________________________________________________________ 5
5 Page 
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Compact, Low-Cost 1S/2S Fuel Gauges
with Low-Battery Alert
2-Wire Bus System
The 2-wire bus system supports operation as a slave-
only device in a single or multislave, and single or multi-
master system. Slave devices can share the bus by
uniquely setting the 7-bit slave address. The 2-wire
interface consists of a serial-data line (SDA) and serial-
clock line (SCL). SDA and SCL provide bidirectional
communication between the MAX17043/MAX17044
slave device and a master device at speeds up to
400kHz. The MAX17043/MAX17044s’ SDA pin operates
bidirectionally; that is, when the MAX17043/MAX17044
receive data, SDA operates as an input, and when the
MAX17043/MAX17044 return data, SDA operates as an
open-drain output, with the host system providing a
resistive pullup. The MAX17043/MAX17044 always
operate as a slave device, receiving and transmitting
data under the control of a master device. The master
initiates all transactions on the bus and generates the
SCL signal, as well as the START and STOP bits, which
begin and end each transaction.
Bit Transfer
One data bit is transferred during each SCL clock
cycle, with the cycle defined by SCL transitioning low-
to-high and then high-to-low. The SDA logic level must
remain stable during the high period of the SCL clock
pulse. Any change in SDA when SCL is high is inter-
preted as a START or STOP control signal.
Bus Idle
The bus is defined to be idle, or not busy, when no
master device has control. Both SDA and SCL remain
high when the bus is idle. The STOP condition is the
proper method to return the bus to the idle state.
START and STOP Conditions
The master initiates transactions with a START condi-
tion (S) by forcing a high-to-low transition on SDA while
SCL is high. The master terminates a transaction with a
STOP condition (P), a low-to-high transition on SDA
while SCL is high. A Repeated START condition (Sr)
can be used in place of a STOP then START sequence
to terminate one transaction and begin another without
returning the bus to the idle state. In multimaster sys-
tems, a Repeated START allows the master to retain
control of the bus. The START and STOP conditions are
the only bus activities in which the SDA transitions
when SCL is high.
Acknowledge Bits
Each byte of a data transfer is acknowledged with an
acknowledge bit (A) or a no-acknowledge bit (N). Both
the master and the MAX17043 slave generate acknowl-
edge bits. To generate an acknowledge, the receiving
device must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low until SCL returns low. To generate a no-
acknowledge (also called NAK), the receiver releases
SDA before the rising edge of the acknowledge-related
clock pulse and leaves SDA high until SCL returns low.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer can occur if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master should reattempt
communication.
Data Order
A byte of data consists of 8 bits ordered most signifi-
cant bit (MSb) first. The least significant bit (LSb) of
each byte is followed by the acknowledge bit. The
MAX17043/MAX17044 registers composed of multibyte
values are ordered MSb first. The MSb of multibyte reg-
isters is stored on even data-memory addresses.
Slave Address
A bus master initiates communication with a slave
device by issuing a START condition followed by a
slave address (SAddr) and the read/write (R/W) bit.
When the bus is idle, the MAX17043/MAX17044 contin-
uously monitor for a START condition followed by its
slave address. When the MAX17043/MAX17044
receive a slave address that matches the value in the
slave address register, they respond with an acknowl-
edge bit during the clock period following the R/W bit.
The 7-bit slave address is fixed to 6Ch (write)/
6Dh (read):
MAX17043/MAX17044
SLAVE ADDRESS
0110110
Read/Write Bit
The R/W bit following the slave address determines the
data direction of subsequent bytes in the transfer. R/W
= 0 selects a write transaction, with the following bytes
being written by the master to the slave. R/W = 1
selects a read transaction, with the following bytes
being read from the slave by the master. (Table 5).
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet MAX17043.PDF ] | |
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