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PDF MAX17040 Data sheet ( Hoja de datos )
| Número de pieza | MAX17040 | |
| Descripción | Low-Cost 1S/2S Fuel Gauges | |
| Fabricantes | Maxim Integrated Products | |
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19-5210; Rev 3; 4/10
EVAALVUAAILTAIOBNLEKIT
www.DataSheet4U.com
Compact, Low-Cost 1S/2S Fuel Gauges
General Description
The MAX17040/MAX17041 are ultra-compact, low-cost,
host-side fuel-gauge systems for lithium-ion (Li+) batter-
ies in handheld and portable equipment. The MAX17040
is configured to operate with a single lithium cell and the
MAX17041 is configured for a dual-cell 2S pack.
The MAX17040/MAX17041 use a sophisticated Li+ bat-
tery-modeling scheme, called ModelGauge™ to track
the battery’s relative state-of-charge (SOC) continuously
over a widely varying charge/discharge profile. Unlike
traditional fuel gauges, the ModelGauge algorithm elim-
inates the need for battery relearn cycles and an exter-
nal current-sense resistor. Temperature compensation
is possible in the application with minimal interaction
between a µC and the device.
A quick-start mode provides a good initial estimate of
the battery’s SOC. This feature allows the IC to be
located on system side, reducing cost and supply
chain constraints on the battery. Measurement and esti-
mated capacity data sets are accessed through an I2C
interface. The MAX17040/MAX17041 are available in a
small, 2mm x 3mm, 8-pin TDFN lead-free package.
Applications
Smart Phones
MP3 Players
Digital Still Cameras
Digital Video Cameras
Portable DVD Players
GPS Systems
Handheld and Portable
Applications
ModelGauge is a trademark of Maxim Integrated Products, Inc.
Pin Configuration
Features
o Host-Side or Battery-Side Fuel Gauging
1 Cell (MAX17040)
2 Cell (MAX17041)
o Precision Voltage Measurement
±12.5mV Accuracy to 5.00V (MAX17040)
±30mV Accuracy to 10.00V (MAX17041)
o Accurate Relative Capacity (RSOC) Calculated
from ModelGauge Algorithm
o No Offset Accumulation on Measurement
o No Full-to-Empty Battery Relearning Necessary
o No Sense Resistor Required
o 2-Wire Interface
o Low Power Consumption
o Tiny, Lead-Free, 8-Pin, 2mm x 3mm TDFN
Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX17040G+U
-20°C to +70°C
8 TDFN-EP*
MAX17040G+T
-20°C to +70°C
8 TDFN-EP*
MAX17041G+U
-20°C to +70°C
8 TDFN-EP*
MAX17041G+T
-20°C to +70°C
8 TDFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
T =Tape and reel.
*EP = Exposed pad.
Simplified Operating Circuit
TOP VIEW
SDA SCL EO SEO
8765
MAX17040
MAX17041
+
1 234
CTG CELL VDD GND
TDFN
(2mm × 3mm)
150Ω
Li+
PROTECTION
CIRCUIT
1µF
CELL
VDD
MAX17040
MAX17041
SEO
EO
CTG SDA
GND EP SCL
150Ω
SYSTEM
µP
I2C BUS
MASTER
10nF
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
1 page  
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Compact, Low-Cost 1S/2S Fuel Gauges
Pin Description
PIN NAME
FUNCTION
1
CTG
Connect to Ground. Connect to VSS during normal operation.
2
CELL
Battery Voltage Input. The voltage of the cell pack is measured through this pin.
3
VDD
Power-Supply Input. 2.5V to 4.5V input range. Connect to system power through a decoupling
network. Connect a 10nF typical decoupling capacitor close to pin.
4
GND
Ground. Connect to the negative power rail of the system.
External 32kHz Clocking Signal Enable Input. Input to enable external clocking signal on EO pin
5 SEO with a pullup state. A pulldown state to configure the interrupt feature. External 32kHz clock
enable. Connects logic-low to enable external interrupt.
6 EO External 32kHz Clocking Signal. Input for external clocking signal to be the primary system clock.
Configured to implement interrupt feature with a pulldown set on SEO pin.
7 SCL Serial Clock Input. Input only 2-wire clock line. Connect this pin to the CLOCK signal of the 2-wire
interface. This pin has a 0.2µA typical pulldown to sense disconnection.
8
SDA
Serial Data Input/Output. Open-drain 2-wire data line. Connect this pin to the DATA signal of the
2-wire interface. This pin has a 0.2µA typical pulldown to sense disconnection.
— EP Exposed Pad. Connect PD to ground.
SDA
tF tF
tSU:DAT
tLOW tR
tHD:STA
tSP tR
tBUF
SCL
tHD:STA
S tHD:DAT
Figure 1. 2-Wire Bus Timing Diagram
VDD
BIAS
TIME BASE
(32kHz)
VOLTAGE
REFERENCE
ADC (VCELL)
MAX17040
MAX17041
STATE
MACHINE
(SOC, RATE)
CELL IC
GND
GROUND
2-WIRE
INTERFACE
Figure 2. Block Diagram
tSU:STA
Sr
tSU:STO
P
S
Detailed Description
Figure 1 shows the 2-wire bus timing diagram, and
EO Figure 2 is the MAX17040/MAX17041 block diagram.
SEO ModelGauge Theory of Operation
CTG The MAX17040/MAX17041 use a sophisticated battery
model, which determines the SOC of a nonlinear Li+
battery. The model effectively simulates the internal
dynamics of a Li+ battery and determines the SOC. The
SDA model considers the time effects of a battery caused by
SCL the chemical reactions and impedance in the battery.
The MAX17040/MAX17041 SOC calculation does not
accumulate error with time. This is advantageous
_______________________________________________________________________________________ 5
5 Page 
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Compact, Low-Cost 1S/2S Fuel Gauges
Table 5. 2-Wire Protocol Key
KEY
S
SAddr
MAddr
Data
A
N
DESCRIPTION
START bit
Slave address (7 bit)
Memory address byte
Data byte written by master
Acknowledge bit—master
No acknowledge—master
KEY
Sr
W
P
Data
A
N
DESCRIPTION
Repeated START
R/W bit = 0
STOP bit
Data byte returned by slave
Acknowledge bit—slave
No acknowledge—slave
Basic Transaction Formats
Write: S. SAddr W. A. MAddr. A. Data0. A. Data1. A. P
A write transaction transfers 2 or more data bytes to the
MAX17040/MAX17041. The data transfer begins at the
memory address supplied in the MAddr byte. Control of
the SDA signal is retained by the master throughout the
transaction, except for the acknowledge cycles:
Read: S. SAddr W. A. MAddr. A. Sr. SAddr R. A. Data0. A. Data1. N. P
Write Portion
Read Portion
A read transaction transfers 2 or more bytes from the
MAX17040/MAX17041. Read transactions are com-
posed of two parts, a write portion followed by a read
portion, and are therefore inherently longer than a write
transaction. The write portion communicates the starting
point for the read operation. The read portion follows
immediately, beginning with a Repeated START, Slave
Address with R/W set to a 1. Control of SDA is assumed
by the MAX17040/MAX17041, beginning with the Slave
Address Acknowledge cycle. Control of the SDA signal
is retained by the MAX17040/MAX17041 throughout the
transaction, except for the acknowledge cycles. The
master indicates the end of a read transaction by
responding to the last byte it requires with a no
acknowledge. This signals the MAX17040/MAX17041
that control of SDA is to remain with the master following
the acknowledge clock.
Write Data Protocol
The write data protocol is used to write to register to the
MAX17040/MAX17041 starting at memory address
MAddr. Data0 represents the data written to MAddr,
Data1 represents the data written to MAddr + 1, and
DataN represents the last data byte, written to MAddr +
N. The master indicates the end of a write transaction
by sending a STOP or Repeated START after receiving
the last Acknowledge bit:
SAddr W. A. MAddr. A. Data0. A. Data1. A... DataN. A
The MSB of the data to be stored at address MAddr
can be written immediately after the MAddr byte is
acknowledged. Because the address is automatically
incremented after the LSB of each byte is received by
the MAX17040/MAX17041, the MSB of the data at
address MAddr + 1 can be written immediately after
the acknowledgment of the data at address MAddr. If
the bus master continues an autoincremented write
transaction beyond address 4Fh, the MAX17040/
MAX17041 ignore the data. A valid write must include
both register bytes. Data is also ignored on writes to
read-only addresses. Incomplete bytes and bytes that
are not acknowledged by the MAX17040/MAX17041
are not written to memory.
Read Data Protocol
The read data protocol is used to read to register from
the MAX17040/MAX17041 starting at the memory
address specified by MAddr. Both register bytes must
be read in the same transaction for the register data to
be valid. Data0 represents the data byte in memory
location MAddr, Data1 represents the data from MAddr
+ 1, and DataN represents the last byte read by the
master:
S. SAddr W. A. MAddr. A. Sr. SAddr R. A.
Data0. A. Data1. A... DataN. N. P
Data is returned beginning with the MSB of the data in
MAddr. Because the address is automatically incre-
mented after the LSB of each byte is returned, the MSB
of the data at address MAddr + 1 is available to the
host immediately after the acknowledgment of the data
at address MAddr. If the bus master continues to read
beyond address FFh, the MAX17040/MAX17041 output
data values of FFh. Addresses labeled Reserved in the
memory map return undefined data. The bus master
terminates the read transaction at any byte boundary
by issuing a no acknowledge followed by a STOP or
Repeated START.
______________________________________________________________________________________ 11
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet MAX17040.PDF ] | |
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