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PDF LTC2757 Data sheet ( Hoja de datos )
| Número de pieza | LTC2757 | |
| Descripción | 18-Bit SoftSpan IOUT DAC | |
| Fabricantes | Linear Technology | |
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www.DataSheet4U.com
LTC2757
18-Bit SoftSpan IOUT DAC
with Parallel I/O
FEATURES
n Maximum 18-Bit INL Error: ±1 LSB Over Temperature
n Program or Pin-Strap Six Output Ranges:
0V to 5V, 0V to 10V, –2.5V to 7.5V, ±2.5V, ±5V, ±10V
n Guaranteed Monotonic Over Temperature
n Low Glitch Impulse 1.4nV•s (3V), 3nV•s (5V)
n 18-Bit Settling Time: 2.1μs
n 2.7V to 5.5V Single Supply Operation
n Reference Current Constant for All Codes
n Voltage-Controlled Offset and Gain Trims
n Parallel Interface with Readback of All Registers
n Clear and Power-On-Reset to 0V Regardless of
Output Range
n 48-Pin 7mm × 7mm LQFP Package
APPLICATIONS
n Instrumentation
n Medical Devices
n Automatic Test Equipment
n Process Control and Industrial Automation
DESCRIPTION
The LTC®2757 is an 18-bit multiplying parallel-input, cur-
rent-output digital-to-analog converter that provides full 18-
bit performance—INL and DNL of ±1LSB maximum—over
temperature without any adjustments. 18-bit monotonicity
is guaranteed in all performance grades. This SoftSpan™
DAC operates from a single 3V to 5V supply and offers
six output ranges (up to ±10V) that can be programmed
through the parallel interface or pin-strapped for operation
in a single range.
In addition to its precision DC specifications, the LTC2757
also offers excellent AC specifications, including 2.1μs
full-scale settling to 1LSB and 1.4nV•s glitch impulse.
The LTC2757 uses a bidirectional input/output parallel
interface that allows readback of any on-chip register,
including DAC output-range settings; and a CLR pin and
power-on reset circuit that each reset the DAC output to
0V regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
18-Bit Voltage Output DAC with Software-Selectable Ranges
REF
5V
+
LT1012
– 150pF
RIN RCOM
REF ROFS RFB
WR
UPD
READ
D/S
CLR
WR LTC2757
IOUT1
UPD
READ
18-BIT DAC WITH SPAN SELECT
IOUT2
D/S GND
CLR
M-SPAN GEADJ
VOSADJ VDD
2757 TA01
GAIN
ADJUST
SPAN I/O
S2-S0
DATA I/O
D17-D0
OFFSET
ADJUST
27pF
–
LT1468
+
0.1μF
5V
LTC2757 Integral Nonlinearity
1.0
±10V RANGE
0.8
0.6
0.4
0.2
0
–0.2
–0.4
VOUT
–0.6
–0.8
–1.0
0
65536
131072
CODE
90°C
25°C
–45°C
196608 262143
2757 TA01b
2757f
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LTC2757
TIMING CHARACTERISTICS VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that
apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
SYMBOL PARAMETER
CLR Timing
CONDITIONS
MIN TYP MAX UNITS
t25 CLR Pulse Width Low
l 20
ns
VDD = 2.7V to 3.3V
Write and Update Timing
t1 I/O Valid to WR Rising Edge Set-Up
t2 I/O Valid to WR Rising Edge Hold
t3 WR Pulse Width
l 18
l 18
l 30
ns
ns
ns
t4 UPD Pulse Width
t5 UPD Falling Edge to WR Falling Edge No Data Shoot-Through
t6 WR Rising Edge to UPD Rising Edge (Note 12)
t7 D/S Valid to WR Falling Edge Set-Up Time
t8 WR Rising Edge to D/S Valid Hold Time
l 30
l0
l0
l 18
l 18
ns
ns
ns
ns
ns
Readback Timing
t13 WR Rising Edge to Read Rising Edge
t14 Read Falling Edge to WR Falling Edge
(Note 12)
l 18
l 40
ns
ns
t15
Read Rising Edge to I/O Propagation Delay
CL = 10pF
l 48 ns
t17 UPD Valid to I/O Propagation Delay
t18 D/S Valid to Read Rising Edge
CL = 10pF
(Note 12)
l
l 18
48 ns
ns
t19 Read Rising Edge to UPD Rising Edge No Update
l9
ns
t20 UPD Falling Edge to Read Falling Edge No Update
l9
ns
t22
READ Falling Edge to UPD Rising Edge
(Note 12)
l 18
ns
t23 I/O Bus Hi-Z to Read Rising Edge
(Note 12)
l0
ns
t24 Read Falling Edge to I/O Bus Active
CLR Timing
(Note 12)
l 40
ns
t25 CLR Pulse Width Low
l 30
ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Continuous operation above the specified maximum operating
junction temperature may impair device reliability.
Note 3: Temperature Coefficient is calculated by dividing the maximum
change in the parameter by the specified temperature range.
Note 4: R1 is measured from RIN to RCOM; R2 is measured from REF to
RCOM.
Note 5: Parallel combination of the resistances from REF to IOUT1 and from
REF to IOUT2. DAC input resistance is independent of code.
Note 6: Because of the proprietary SoftSpan switching architecture, the
measured resistance looking into each of the specified pins is constant for
all output ranges if the IOUT1 and IOUT2 pins are held at ground.
Note 7: Using LT1468 with CFEEDBACK = 27pF. A ±0.0004% settling time
of 1.8μs can be achieved by optimizing the time constant on an individual
basis. See Application Note 120, 1ppm Settling Time Measurement for a
Monolithic 18-Bit DAC.
Note 8: Measured at the major carry transition, 0V to 5V range. Output
amplifier: LT1468; CFB = 50pF.
Note 9: Zero-code to full-code transition; REF = 0V. Falling transition is
similar or better.
Note 10: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output
amplifier = LT1468.
Note 11: Calculation from Vn = √4kTRB, where k = 1.38E-23 J/°K
(Boltzmann constant), R = resistance (Ω), T = temperature (°K), and B =
bandwidth (Hz).
Note 12: Guaranteed by design. Not production tested.
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LTC2757
OPERATION
Output Ranges
The LTC2757 is a current-output, parallel-input precision
multiplying DAC offering ±1LSB INL and DNL over six
software-selectable output ranges. Ranges can either
be programmed in software for maximum flexibility or
hardwired through pin-strapping. Two unipolar ranges
are available (0V to 5V and 0V to 10V), and four bipolar
ranges (±2.5V, ±5V, ±10V and –2.5V to 7.5V). These ranges
are obtained when an external precision 5V reference is
used. The output ranges for other reference voltages
are easy to calculate by observing that each range is a
multiple of the external reference voltage. The ranges can
then be expressed: 0 to 1×, 0 to 2×, ±0.5×, ±1×, ±2×, and
–0.5× to 1.5×.
Digital Section
The LTC2757 has four internal interface registers (see
Block Diagram). Two of these—one Input and one DAC
register—are dedicated to the Data I/O port, and two
to the Span I/O port. Each port is thus double buffered.
Double buffering provides the capability to simultaneously
update the Span and Code registers, which allows smooth
voltage transitions when changing output ranges. It also
permits the simultaneous updating of multiple DACs or
other parts on the data bus.
Write and Update Operations
Load the data input register directly from an 18-bit bus
by holding the D/S pin low and then pulsing the WR pin
low (Write operation).
Load the Span Input register by holding the D/S pin high
and then pulsing the WR pin low (Write operation). The
Span and Data register structures are the same except for
the number of parallel bits—the Span registers have three
bits, while the Data registers have 18 bits.
The DAC registers are loaded by pulsing the UPD pin
high (Update operation), which copies the data held in
the Input registers of both ports into the DAC registers.
Note that Update operations always include both Data
and Span registers; but the DAC register values will not
change unless the Input register values have previously
been changed by a Write operation.
To make both registers transparent for flowthrough
mode, tie WR low and UPD high. However, this defeats
the deglitcher operation and output glitch impulse may
increase. The deglitcher is activated on the rising edge
of the UPD pin.
The interface also allows the use of the Input and DAC
registers in a master-slave, or edge-triggered, configura-
tion. This mode of operation occurs when WR and UPD
are tied together and driven by a single clock signal. The
data bits are loaded into the Input register on the falling
edge of the clock and then loaded into the DAC register
on the rising edge.
It is possible to control both ports on one 18-bit wide
data bus by allowing Span pins S2 to S0 to share bus
lines with the Data LSBs (D2 to D0). No Write or Read
operation acts on both span and data, so there cannot be
a signal conflict.
The asynchronous clear pin (CLR) resets the LTC2757
to 0V (zero-, half- or quarter-scale code) in any output
range. CLR resets both the Input and DAC data registers,
but leaves the Span registers unchanged.
The device also has a power-on reset that initializes the DAC
to VOUT = 0V in any output range. The DAC powers up in
the 0V to 5V range at zero-scale if the part is in SoftSpan
configuration. For manual span (M-SPAN tied to VDD; see
Manual Span Configuration), the DACs power-up in the
manually-chosen range at the appropriate code.
Manual Span Configuration
Multiple output ranges are not needed in some applica-
tions. To configure the LTC2757 for single-span opera-
tion, tie the M-SPAN pin to VDD and the D/S pin to GND.
The desired output range is programmed by tying S0,
S1 and S2 to GND or VDD (see Figure 1 and Table 2). In
this configuration, no range-setting software routine is
needed; the part will initialize to the chosen output range
at power-up, with VOUT = 0V.
When configured for manual span operation, Span port
readback is disabled.
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| PDF Descargar | [ Datasheet LTC2757.PDF ] | |
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